Index: /branches/RWT/soft/validation/Makefile =================================================================== --- /branches/RWT/soft/validation/Makefile (revision 843) +++ /branches/RWT/soft/validation/Makefile (revision 843) @@ -0,0 +1,6 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x term* Index: /branches/RWT/soft/validation/scripts/Makefile.nat =================================================================== --- /branches/RWT/soft/validation/scripts/Makefile.nat (revision 843) +++ /branches/RWT/soft/validation/scripts/Makefile.nat (revision 843) @@ -0,0 +1,6 @@ + +all: test_natif + +test_natif: gen_test.c + gcc -o $@ $< -lpthread + Index: /branches/RWT/soft/validation/scripts/TestGenerator/EnsembleVariables.hpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/EnsembleVariables.hpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/EnsembleVariables.hpp (revision 843) @@ -0,0 +1,218 @@ + +#ifndef _ensemblevariables_hpp_ +#define _ensemblevariables_hpp_ + +#include "functions.h" +#include "Variable.hpp" + +#include +#include +#include +#include + +using namespace std; + +class EnsembleVariables { + + int nb_vars; + int nb_procs; + int nb_diff_CL; + int cache_lines; + int line_size; + int nb_lines_uncached; + int tab_size_digits; + Variable * LesVariables; + + void setnPubROWO(int n, int mode) { + // mode = 0 : -> RO; mode = 1 : -> WO; mode = 2 -> Private + // Les seules variables pouvant être mises en RO, en WO ou en private sont les variables publiques RW + int nb_pub_rw = 0; + for (int i = 0; i < nb_vars; i++) { + if (LesVariables[i].getProc() == -1 && LesVariables[i].isRW()) { + nb_pub_rw += 1; + } + } + if (n > nb_pub_rw) { + fprintf(stderr,"Error in function %s: cannot change attribute on as many variables\n",__func__); + } + int index; + int index_to_set; + for (int i = 0; i < n; i++) { + index = randint(0,nb_pub_rw - 1); + index_to_set = 0; + for (int j = 0; j < index; j++) { + index_to_set++; + while (LesVariables[index_to_set].getProc() != -1 || !LesVariables[index_to_set].isRW()) { + index_to_set++; + } + } + + if (mode == 0) { + LesVariables[index_to_set].setRO(); + } + else if (mode == 1) { + LesVariables[index_to_set].setWO(); + } + else { + assert(mode == 2); + int proc = randint(0,nb_procs - 1); + LesVariables[index_to_set].setPrivate(proc); + } + nb_pub_rw--; + } + + } + + public: + + EnsembleVariables(int nb_vars, int nb_procs, int nb_diff_CL, int cache_lines, int line_size, int nb_lines_uncached, int tab_size) { + this->nb_vars = nb_vars; + this->nb_procs = nb_procs; + this->nb_diff_CL = nb_diff_CL; + this->cache_lines = cache_lines; + this->line_size = line_size; + this->nb_lines_uncached = nb_lines_uncached; + this->tab_size_digits = (int) ceil(log10(tab_size)); + LesVariables = new Variable[nb_vars + nb_lines_uncached*line_size]; + for (int i = nb_vars; i < nb_vars + nb_lines_uncached * line_size; i++) { + LesVariables[i].setUncached(); + LesVariables[i].setROorWO(); + } + } + + void setnPubRO(int n) { + setnPubROWO(n, 0); + } + + void setnPubWO(int n) { + setnPubROWO(n, 1); + } + + void setnPrivate(int n) { + setnPubROWO(n, 2); + } + + void setnPrivROWO(void) { + // change les variables privées en RO ou WO, avec une probabilité de 20% pour chaque + // Eventuellement changer l'interface en : changer strictement n variables privées en RO ou WO, comme pour le cas public + for (int i = 0; i < nb_vars; i++) { + if (LesVariables[i].getProc() != -1 && LesVariables[i].isRW()) { + int r = randint(1,5); + if (r == 1) { + LesVariables[i].setRO(); + } + else if (r == 2) { + LesVariables[i].setWO(); + } + } + } + } + + string writeVariablesNature() { + assert(nb_vars % line_size == 0); + + stringstream res; + res << "/*******************" << endl; + res << "* Variables Nature *" << endl; + res << "*******************/" << endl; + + for (int i = 0; i < (nb_vars / line_size) + nb_lines_uncached; i++) { + if (i == 0) { + res << "/*"; + } + else { + res << " *"; + } + for (int j = 0; j < line_size; j++) { + int var_index = i * line_size + j; + int tab_index = index2realindex(var_index, nb_diff_CL, cache_lines, line_size); + res << " [" << setw(tab_size_digits) << tab_index << "]"; + if (LesVariables[var_index].isPublic()) { + res << "Pub "; + } + else { + res << setw(3) << LesVariables[var_index].getProc() << " "; + } + if (LesVariables[var_index].isRW()) { + res << "RW "; + } + else if (LesVariables[var_index].isRO()) { + res << "RO "; + } + else { + assert(LesVariables[var_index].isWO()); + res << "WO "; + } + if (LesVariables[var_index].isUnc()) { + res << "(U)"; + } + else { + res << " "; + } + } + res << endl; + } + res << " */" << endl; + return res.str(); + } + + string writePrivateAccesses(int proc_id) { + stringstream res; + for (int i = 0; i < nb_vars; i++) { + int tab_index = index2realindex(i, nb_diff_CL, cache_lines, line_size); + if (LesVariables[i].isPrivate(proc_id)) { + if (LesVariables[i].isRW()) { + res << " tab[" << tab_index << "]++; // variable privee au proc " << proc_id << endl; + } + else if (LesVariables[i].isRO()) { + res << " local_var = tab[" << tab_index << "]; // variable privee au proc " << proc_id << " et en RO" << endl; + } + else { + assert(LesVariables[i].isWO()); + res << " tab[" << tab_index << "] = 1; // variable privee au proc " << proc_id << " et en WO" << endl; + } + } + } + return res.str(); + } + + + int getVarCount(int proc_id) { + // Retourne le nombre de variables pouvant être utilisées par le processeur proc_id + int n = 0; + for (int i = 0; i < nb_vars + nb_lines_uncached * line_size; i++) { + if (LesVariables[i].isPublic() || LesVariables[i].isPrivate(proc_id)) { + n++; + } + } + return n; + } + + bool isPublic(int var_index) { + return LesVariables[var_index].isPublic(); + } + + bool isRW(int var_index) { + return LesVariables[var_index].isRW(); + } + + bool isRO(int var_index) { + return LesVariables[var_index].isRO(); + } + + bool isWO(int var_index) { + return LesVariables[var_index].isWO(); + } + + bool isUnc(int var_index) { + return LesVariables[var_index].isUnc(); + } + + bool isPrivate(int var_index, int proc_id) { + return LesVariables[var_index].isPrivate(proc_id); + } + +}; + +#endif + Index: /branches/RWT/soft/validation/scripts/TestGenerator/Genere_ML_CL.cpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/Genere_ML_CL.cpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/Genere_ML_CL.cpp (revision 843) @@ -0,0 +1,27 @@ + + +#include "functions.h" +#include "time.h" +#include + +int main(int argc, char** argv){ + + srand(time(NULL)); + + if (argc != 2){ + std::cerr << "Erreur" << std::endl; + std::cerr << "Utilisation : genere_ML_CL " << std::endl; + } + + int nb_max = atoi(argv[1]); + if (nb_max <= 0){ + std::cerr << "Erreur : nb_max doit etre superieur ou egal a 1" << std::endl; + } + + int nb = randint(1,nb_max); + + std::cout << nb << std::endl; + + return 0; +} + Index: /branches/RWT/soft/validation/scripts/TestGenerator/Genere_Tests.cpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/Genere_Tests.cpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/Genere_Tests.cpp (revision 843) @@ -0,0 +1,39 @@ + + +#include "Program.hpp" +#include "config.h" + +#include +#include +#include + +int main(int argc, char** argv){ + + if (argc != 9){ + printf("usage: genere_test \n"); + exit(1); + } + + srand(time(NULL)); + + FILE * outfile; + + const int nb_procs = atoi(argv[1]); + const int nb_max_incr = atoi(argv[2]); + const int nb_max_trans = atoi(argv[3]); + const int nb_diff_ML = atoi(argv[4]); + const int nb_diff_CL = atoi(argv[5]); + const int line_size = atoi(argv[6]); + const int nb_cache_lines = atoi(argv[7]); + + outfile = fopen(argv[8], "w"); + + Program prog(nb_procs, nb_diff_ML, nb_diff_CL, nb_max_trans, nb_max_incr, line_size, nb_cache_lines); + + string s = prog.writeOutput(); + fprintf(outfile, "%s", s.c_str()); + fclose(outfile); + + return 0; +} + Index: /branches/RWT/soft/validation/scripts/TestGenerator/Increment.hpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/Increment.hpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/Increment.hpp (revision 843) @@ -0,0 +1,115 @@ + +#ifndef _increment_hpp_ +#define _increment_hpp_ + +#include "functions.h" +#include "EnsembleVariables.hpp" + +#include +#include +#include +#include + +using namespace std; + +class Increment { + int var_index; + int nb_diff_CL; + int cache_lines; + int line_size; + int proc_id; + EnsembleVariables * E; + + public: + + Increment(int nb_diff_ML, int nb_diff_CL, int line_size, int cache_lines, EnsembleVariables * E, int proc_id) { + this->nb_diff_CL = nb_diff_CL; + this->line_size = line_size; + this->cache_lines = cache_lines; + this->E = E; + this->proc_id = proc_id; + + const int nb_vars_proc = E->getVarCount(proc_id); + int local_index = randint(0, nb_vars_proc - 1); + var_index = 0; + while (!E->isPublic(var_index) && !E->isPrivate(var_index,proc_id)) { + var_index++; + } + for (int i = 0; i < local_index; i++) { + var_index++; + while (!E->isPublic(var_index) && !E->isPrivate(var_index,proc_id)) { + var_index++; + } + } + } + + ~Increment() {} + + string writeOutput() { + stringstream res; + int index = index2realindex(var_index, nb_diff_CL, cache_lines, line_size); + if (E->isPublic(var_index)) { + if (!E->isUnc(var_index)) { + if (E->isRW(var_index)) { + res << " pthread_spin_lock(&lock_tab[" << var_index << "]);" << endl; + res << " tab[" << index << "]++;" << endl; + res << " pthread_spin_unlock(&lock_tab[" << var_index << "]);" << endl; + } + else if (E->isRO(var_index)) { + res << " local_var = tab[" << index << "];" << endl; + } + else { + assert(E->isWO(var_index)); + res << " tab[" << index << "] = 1;" << endl; + } + } + else { + if (E->isRW(var_index)) { + res << " rd_wr_unc(" << index << ");" << endl; + } + else if (E->isRO(var_index)) { + res << " rd_unc(" << index << ");" << endl; + } + else { + assert(E->isWO(var_index)); + res << " wr_unc(" << index << ");" << endl; + } + } + } + else { + assert(E->isPrivate(var_index,proc_id)); + if (!E->isUnc(var_index)) { + if (E->isRW(var_index)) { + res << " tab[" << index << "]++; // variable privee au proc " << proc_id << endl; + } + else if (E->isRO(var_index)) { + res << " local_var = tab[" << index << "]; // variable privee au proc " << proc_id << " et en RO" << endl; + } + else { + assert(E->isWO(var_index)); + res << " tab[" << index << "] = 1; // variable privee au proc " << proc_id << " et en WO" << endl; + } + } + else { + if (E->isRW(var_index)) { + res << " // Variable privee au proc " << proc_id << endl; + res << " rd_wr_unc(" << index << ");" << endl; + } + else if (E->isRO(var_index)) { + res << " // Variable privee au proc " << proc_id << " et en RO" << endl; + res << " rd_unc(" << index << ");" << endl; + } + else { + assert(E->isWO(var_index)); + res << " // Variable privee au proc " << proc_id << " et en WO" << endl; + res << " wr_unc(" << index << ");" << endl; + } + } + } + return res.str(); + } + +}; + +#endif + Index: /branches/RWT/soft/validation/scripts/TestGenerator/Makefile =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/Makefile (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/Makefile (revision 843) @@ -0,0 +1,14 @@ + +HPP_FILES=$(wildcard *.hpp) + + +all: generate_test generate_ML_CL + +generate_test: Genere_Tests.cpp $(HPP_FILES) config.h + g++ -o $@ $< + +generate_ML_CL: Genere_ML_CL.cpp + g++ -o $@ $< + +clean: + rm generate_test generate_ML_CL Index: /branches/RWT/soft/validation/scripts/TestGenerator/Program.hpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/Program.hpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/Program.hpp (revision 843) @@ -0,0 +1,262 @@ + +#ifndef _program_hpp_ +#define _program_hpp_ + +#include "config.h" +#include "TestThread.hpp" +#include "EnsembleVariables.hpp" + +#include +#include + +using namespace std; + +class Program { + + int nb_lines_uncached; + int nb_threads; + int tab_size; + int nb_diff_ML, nb_diff_CL, line_size, cache_lines; + EnsembleVariables * E; + TestThread** threads; + + public: + + Program(int nb_procs, int nb_diff_ML, int nb_diff_CL, int nb_max_trans, int nb_max_insts, int line_size, int cache_lines) { + nb_lines_uncached = 1; + nb_threads = nb_procs; + threads = new TestThread*[nb_threads]; + tab_size = (cache_lines * line_size) * ((int) ceil((double) (nb_diff_ML + nb_lines_uncached) / (double) nb_diff_CL) - 1) + (nb_diff_CL * line_size); + this->nb_diff_ML = nb_diff_ML; + this->nb_diff_CL = nb_diff_CL; + this->line_size = line_size; + this->cache_lines = cache_lines; + + E = new EnsembleVariables(nb_diff_ML * line_size, nb_procs, nb_diff_CL, cache_lines, line_size, nb_lines_uncached, tab_size); // tab_size passed for format printing + + E->setnPubRO(nb_diff_ML); + E->setnPubWO(nb_diff_ML); + E->setnPrivate(nb_diff_ML); + E->setnPrivROWO(); + + for (int i = 0; i < nb_threads; i++) { + threads[i] = new TestThread(nb_diff_ML, nb_diff_CL, nb_max_trans, nb_max_insts, line_size, cache_lines, E, i); + } + } + + ~Program() { + for (int i = 0; i < nb_threads; i++) { + delete threads[i]; + } + delete [] threads; + delete E; + } + + string writeOutput() { + stringstream res; + res << endl; + res << "#include " << endl; + res << "#include " << endl; + res << "#include " << endl; + res << endl; + + res << "#ifdef _ALMOS_" << endl; + res << "#define rd_wr_unc(index) ({ \\" << endl; + res << " asm volatile( \\" << endl; + res << " \"li $8, \" #index \"\\n\" \\" << endl; + res << " \"sll $8, $8, 2\\n\" \\" << endl; + res << " \"addu $8, $8, %0\\n\" \\" << endl; + res << " \"li $10, 0xC\\n\" \\" << endl; + //res << " \"mtc2 $10, $1\\n\" \\" << endl; + res << " \"lw $9, 0($8)\\n\" \\" << endl; + res << " \"add $9, $9, 1\\n\" \\" << endl; + res << " \"sw $9, 0($8)\\n\" \\"<< endl; + res << " \"li $10, 0xF\\n\" \\" << endl; + //res << " \"mtc2 $10, $1\\n\" \\" << endl; + res << " : \\" << endl; + res << " : \"r\" (tab) \\" << endl; + res << " : \"$8\", \"$9\", \"$10\"); \\" << endl; + res << "})" << endl; + res << endl; + + res << "#define wr_unc(index) ({ \\" << endl; + res << " asm volatile( \\" << endl; + res << " \"li $8, \" #index \"\\n\" \\" << endl; + res << " \"sll $8, $8, 2\\n\" \\" << endl; + res << " \"addu $8, $8, %0\\n\" \\" << endl; + res << " \"li $10, 0xC\\n\" \\" << endl; + //res << " \"mtc2 $10, $1\\n\" \\" << endl; + res << " \"sw $0, 0($8)\\n\" \\"<< endl; + res << " \"li $10, 0xF\\n\" \\" << endl; + //res << " \"mtc2 $10, $1\\n\" \\" << endl; + res << " : \\" << endl; + res << " : \"r\" (tab) \\" << endl; + res << " : \"$8\", \"$10\"); \\" << endl; + res << "})" << endl; + res << endl; + + res << "#define rd_unc(index) ({ \\" << endl; + res << " asm volatile( \\" << endl; + res << " \"li $8, \" #index \"\\n\" \\" << endl; + res << " \"sll $8, $8, 2\\n\" \\" << endl; + res << " \"addu $8, $8, %0\\n\" \\" << endl; + res << " \"li $10, 0xC\\n\" \\" << endl; + //res << " \"mtc2 $10, $1\\n\" \\" << endl; + res << " \"lw $9, 0($8)\\n\" \\" << endl; + res << " \"li $10, 0xF\\n\" \\" << endl; + //res << " \"mtc2 $10, $1\\n\" \\" << endl; + res << " : \\" << endl; + res << " : \"r\" (tab) \\" << endl; + res << " : \"$8\", \"$9\", \"$10\"); \\" << endl; + res << "})" << endl; + res << endl; + res << "#else" << endl; + res << " #define rd_wr_unc(index) ({ tab[index]++; })" << endl; + res << " #define rd_unc(index) ({ local_var = tab[index]; })" << endl; + res << " #define wr_unc(index) ({ tab[index] = 0; })" << endl; + res << "#endif" << endl; + + res << endl; + res << "#define NB_THREADS " << nb_threads << endl; + res << endl; + res << "/* NB_MAX_TRANS : " << NB_MAX_TRANS << endl; + res << " * NB_MAX_INSTS : " << NB_MAX_INSTS << endl; + res << " * LINE_SIZE : " << LINE_SIZE << endl; + res << " * CACHE_LINES : " << CACHE_LINES << endl; + res << " */" << endl; + res << endl; + res << "volatile int tab[" << tab_size << "];" << endl; + res << endl; + res << "pthread_spinlock_t lock_tab[" << nb_diff_ML * line_size << "];" << endl; + res << endl; + res << E->writeVariablesNature(); + res << endl; + res << endl; + + for (int i = 0; i < nb_threads; i++) { + res << threads[i]->writeOutput(i); + } + + res << "int main() {" << endl; + res << endl; + res << " unsigned int start;" << endl; + res << " unsigned int end;" << endl; + res << " unsigned int result;" << endl; + res << " int i;" << endl; + res << " void (*main_run) (); // fonction run du main" << endl; + res << endl; + res << " #ifdef _ALMOS_" << endl; + res << " printf(\"\\n\");" << endl; + res << " #endif" << endl; + res << endl; + res << " printf(\"dans le main\\n\");" << endl; + res << endl; + res << " for (i = 0; i < " << nb_diff_ML * line_size << "; i++) {" << endl; + res << " pthread_spin_init(&lock_tab[i], 0);" << endl; + res << " }" << endl; + res << " pthread_t** threads;" << endl; + res << " threads = malloc(sizeof(pthread_t *) * NB_THREADS);" << endl; + res << endl; + res << " pthread_attr_t* attr;" << endl; + res << " attr = malloc(sizeof(pthread_attr_t) * NB_THREADS);" << endl; + res << endl; + res << " int my_cpu;" << endl; + res << " #ifdef _ALMOS_" << endl; + res << " pthread_attr_getcpuid_np(&my_cpu);" << endl; + res << " #else" << endl; + res << " my_cpu = NB_THREADS - 1;" << endl; + res << " #endif" << endl; + res << " for (i = 0; i < NB_THREADS; i++) {" << endl; + res << " if (i != my_cpu) { " << endl; + res << " threads[i] = malloc(sizeof(pthread_t));" << endl; + res << " pthread_attr_init(&attr[i]);" << endl; + res << " #ifdef _ALMOS_" << endl; + res << " pthread_attr_setcpuid_np(&attr[i], i, NULL);" << endl; + res << " #endif" << endl; + res << " } " << endl; + res << " }" << endl; + res << endl; + + int index; + for (int i = 0; i < nb_diff_ML * line_size; i++) { + index = index2realindex(i,nb_diff_CL,cache_lines,line_size); + res << " tab[" << index << "] = " << index << ";" << endl; + } + res << endl; + for (int i = 0; i < nb_threads; i++) { + res << " run" << i << "();" << endl; + } + res << endl; + for (int i = 0; i < nb_diff_ML * line_size; i++) { + index = index2realindex(i,nb_diff_CL,cache_lines,line_size); + res << " tab[" << index << "] = " << index << ";" << endl; + } + + //res << " printf("%s --> create run\n",__func__);" << endl; + //res << " start = GetTimeUS();" << endl; + res << endl; + res << " for (i = 0; i < NB_THREADS; i++) {" << endl; + res << " if (i == 0) {" << endl; + res << " if (i != my_cpu) { " << endl; + res << " int error = pthread_create(threads[i], &attr[i], (void *) run0, 0);" << endl; + res << " if (error != 0) {" << endl; + res << " printf(\"*** Error in pthread_create\\n\");" << endl; + res << " }" << endl; + res << " }" << endl; + res << " else {" << endl; + res << " main_run = run0;" << endl; + res << " }" << endl; + res << " }" << endl; + for (int i = 1; i < nb_threads; i++) { + res << " else if (i == " << i << ") {" << endl; + res << " if (i != my_cpu) { " << endl; + res << " int error = pthread_create(threads[i], &attr[i], (void *) run" << i << ", 0);" << endl; + res << " if (error != 0) {" << endl; + res << " printf(\"*** Error in pthread_create\\n\");" << endl; + res << " }" << endl; + res << " }" << endl; + res << " else {" << endl; + res << " main_run = run" << i << ";" << endl; + res << " }" << endl; + res << " }" << endl; + } + res << " else {" << endl; + res << " printf(\"Erreur : pas de fonction run correspondant au threads/processeur %d\\n\",i);" << endl; + res << " }" << endl; + res << " }" << endl; + res << endl; + res << " main_run();" << endl; + res << endl; + res << " for (i = 0; i < NB_THREADS; i++) {" << endl; + res << " if (i != my_cpu) {" << endl; + res << " pthread_join(*threads[i], NULL);" << endl; + res << " }" << endl; + res << " }" << endl; + res << endl; + //res << " end = GetTimeUS();" << endl; + //res << " printf("%s <-- join run\n",__func__);" << endl; + res << endl; + res << " result = end - start;" << endl; + //res << " printf(\"temps ecoule : %u\n\",result);" << endl; + + for (int i = 0; i < nb_diff_ML*line_size; i++) { + index = index2realindex(i,nb_diff_CL,cache_lines,line_size); + res << " printf(\"tab[" << index << "] final : %d\\n\",tab[" << index << "]);" << endl; + } + res << " #ifdef _ALMOS_" << endl; + res << " *(int *) 0x0 = 0xDEADDEAD;" << endl; + res << " #endif" << endl; + res << endl; + res << " return 0;" << endl; + res << "} " << endl; + return res.str(); + } + +}; + +#endif + + + + + Index: /branches/RWT/soft/validation/scripts/TestGenerator/TestThread.hpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/TestThread.hpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/TestThread.hpp (revision 843) @@ -0,0 +1,54 @@ + +#ifndef _testthread_hpp_ +#define _testthread_hpp_ + +#include "Transaction.hpp" +#include "EnsembleVariables.hpp" + +#include +#include + +using namespace std; + +class TestThread { + + std::list requests; + + public: + + TestThread(int nb_diff_ML, int nb_diff_CL, int nb_max_trans, int nb_max_insts, int line_size, int cache_lines, EnsembleVariables * E, int proc_id) { + const int nb_trans = randint(1,nb_max_trans); + for (int i = 0; i < nb_trans; i++){ + Transaction *t; + t = new Transaction(nb_diff_ML,nb_diff_CL,nb_max_insts,line_size,cache_lines,E,proc_id); + requests.push_back(t); + } + } + + ~TestThread() { + std::list::iterator it; + for (it = requests.begin(); it != requests.end(); it++) { + delete (*it); + } + requests.clear(); + } + + string writeOutput(int i) { + stringstream res; + res << "void run" << i << "() {" << endl; + res << " int local_var; // variable pour pouvoir avoir des transactions où l'on ne fait que lire les variables utiles" << endl; + res << endl; + + std::list::iterator it; + for (it = requests.begin(); it != requests.end(); it++) { + res << (*it)->writeOutput(); + } + + res << "}" << endl; + res << endl; + return res.str(); + } + +}; + +#endif Index: /branches/RWT/soft/validation/scripts/TestGenerator/Transaction.hpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/Transaction.hpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/Transaction.hpp (revision 843) @@ -0,0 +1,59 @@ + +#ifndef _transaction_hpp_ +#define _transaction_hpp_ + +#include "Increment.hpp" +#include "EnsembleVariables.hpp" + +#include +#include +#include + +using namespace std; + +class Transaction { + + EnsembleVariables * E; + int proc_id; + std::list requests; + + public: + + Transaction(int nb_diff_ML, int nb_diff_CL, int nb_max_insts, int line_size, int cache_lines, EnsembleVariables * E, int proc_id){ + this->proc_id = proc_id; + this->E = E; + const int nb_insts = randint(1, nb_max_insts); + for (int i = 0; i < nb_insts; i++) { + Increment *incr; + incr = new Increment(nb_diff_ML, nb_diff_CL, line_size, cache_lines, E, proc_id); + requests.push_back(incr); + } + } + + ~Transaction() { + std::list::iterator it; + for (it = requests.begin(); it != requests.end(); it++){ + delete (*it); + } + requests.clear(); + } + + string writeOutput() { + stringstream res; + res << E->writePrivateAccesses(proc_id); + res << " // Debut Transaction" << endl; + + std::list::iterator it; + for (it = requests.begin(); it != requests.end(); it++) { + res << (*it)->writeOutput(); + } + + res << " // Fin Transaction" << endl; + res << endl; + + return res.str(); + } + +}; + +#endif Index: /branches/RWT/soft/validation/scripts/TestGenerator/Variable.hpp =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/Variable.hpp (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/Variable.hpp (revision 843) @@ -0,0 +1,89 @@ + +#ifndef _variable_hpp_ +#define _variable_hpp_ + +#include "assert.h" + +class Variable { + + int proc; // processor to which the variable belongs, -1 if public (most common case) + int operation; // 0 : RW ; 1 : RO ; 2 : WO + bool uncached; // Requests on this variable are done uncached + bool in_trans_line; // if private variable, specifies whether the variable is located in a line containing transactional variables + + public: + + Variable(int proc, int operation, bool uncached, bool in_trans_line = true){ + assert(proc >= -1); + assert(operation == 0 || operation == 1 || operation == 2); + assert(in_trans_line || proc != -1); + this->proc = proc; + this->operation = operation; + this->uncached = uncached; + this-> in_trans_line = in_trans_line; + } + + Variable(){ + this->proc = -1; + this->operation = 0; + this->uncached = false; + this->in_trans_line = true; + } + + int getProc(){ + return proc; + } + + bool isRW(){ + return (operation == 0); + } + + bool isRO(){ + return (operation == 1); + } + + bool isWO(){ + return (operation == 2); + } + + bool isUnc(){ + return uncached; + } + + void setRO(){ + operation = 1; + } + + void setWO(){ + operation = 2; + } + + void setROorWO(){ + int n = randint(1,2); + if (n == 1){ + operation = 1; + } + else { + operation = 2; + } + } + + void setPrivate(int proc_id){ + proc = proc_id; + } + + void setUncached(){ + uncached = true; + } + + bool isPublic(){ + return (proc == -1); + } + + bool isPrivate(int proc_id){ + return (proc == proc_id); + } + +}; + +#endif Index: /branches/RWT/soft/validation/scripts/TestGenerator/config.h =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/config.h (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/config.h (revision 843) @@ -0,0 +1,11 @@ + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#define NB_MAX_TRANS 40 +#define NB_MAX_INSTS 20 +#define LINE_SIZE 16 +#define CACHE_LINES 256 + +#endif + Index: /branches/RWT/soft/validation/scripts/TestGenerator/functions.h =================================================================== --- /branches/RWT/soft/validation/scripts/TestGenerator/functions.h (revision 843) +++ /branches/RWT/soft/validation/scripts/TestGenerator/functions.h (revision 843) @@ -0,0 +1,37 @@ + +#ifndef _functions_h_ +#define _functions_h_ + +#include +#include +#include + + +static int mylog2(size_t v) { + static const size_t b[] = { 0x2, 0xC, 0xF0, 0xFF00, 0xFFFF0000 }; + static const size_t S[] = { 1, 2, 4, 8, 16 }; + int i; + register size_t r = 0; + for (i = 4; i >= 0; i--) { + if (v & b[i]) { + v >>= S[i]; + r |= S[i]; + } + } + return r + 1; +} + +int randint(int a, int b) { + int range = b - a + 1; + int res = rand() % range; + return res + a; +} + + +int index2realindex(int var_index, int nb_diff_CL, int cache_lines, int line_size) { + int index = var_index % (nb_diff_CL * line_size) + (cache_lines * line_size)*(var_index / (line_size * nb_diff_CL)); + return index; +} + + +#endif Index: /branches/RWT/soft/validation/scripts/gen_arch_info_large.sh =================================================================== --- /branches/RWT/soft/validation/scripts/gen_arch_info_large.sh (revision 843) +++ /branches/RWT/soft/validation/scripts/gen_arch_info_large.sh (revision 843) @@ -0,0 +1,236 @@ +#! /bin/bash + +#-------------------------------------------------------------------- +# File : gen_arch_info_large.sh +#-------------------------------------------------------------------- + +NB_TTY=4 +TTY_CHANNEL_SIZE=0x10 +TTY_SIZE=0x1000 + +DMA_SIZE=0x1000 +XICU_SIZE=0x1000 +BDEV_SIZE=0x1000 +# FrameBuffer size +#FB_SIZE=0x80000 +FB_SIZE=0x200000 + +MEMC_TGTID=0 +XICU_TGTID=1 +MDMA_TGTID=2 +MTTY_TGTID=3 +BDEV_TGTID=4 +MNIC_TGTID=5 +BROM_TGTID=6 +CDMA_TGTID=7 +SIMH_TGTID=8 +FBUF_TGTID=9 + + +# Physical address width +ADDR_WIDTH=32 + +# Default values +DEFAULT_X_MAX=8 +DEFAULT_Y_MAX=8 +DEFAULT_CPU_PER_CLUSTER=4 + +function mymin() +{ + if test $1 -lt $2 ; then + echo "$1" + else + echo "$2" + fi +} + +#------------------------ + +X_MAX=${1-$DEFAULT_X_MAX} +Y_MAX=${2-$DEFAULT_Y_MAX} +NPROCS=$DEFAULT_CPU_PER_CLUSTER + +#------------------------ +CLUSTER_INC=$((0x80000000 / (X_MAX * Y_MAX) * 2)) +MAX_MEMC_SIZE=$((0x40000000 / (X_MAX * Y_MAX))) +size=$(mymin $MAX_MEMC_SIZE $((0x04000000))) +MEMC_SIZE=$(printf "0x%X" $size) + + +print_comments() +{ + date=$(date "+%c") + echo "# TSAR hardware description in BIB (Boot Information Block) format" + echo "# This file is autogenerated by the command: $0 $X_MAX $Y_MAX $NPROCS $BSCPU" + echo "# It is ready to be passed to info2bib utility so the binary format can be generated" + echo " " + echo "# $USER on $HOSTNAME $date" + echo " " + echo " " +} + +print_header() +{ + echo "[HEADER]" + echo " REVISION=1" + echo " ARCH=SOCLIB-TSAR" + echo " XMAX=$X_MAX" + echo " YMAX=$Y_MAX" + echo " CPU_NR=$NPROCS" + echo " BSCPU=$BSCPU" + echo " BSTTY=$BSTTY" + echo " BSDMA=$BSDMA" + echo " " + echo " " +} + +print_cluster() +{ + offset=$1 + cid=$2 + memc_base=$(printf "0x%X" $offset) + memc_size=$(printf "0x%X" $MEMC_SIZE) + xicu_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (XICU_TGTID << 19)))) + dma_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)))) + + echo "[CLUSTER]" + echo " CID="$cid + echo " CPU_NR="$NPROCS + echo " DEV_NR=3" + echo " DEVID=RAM BASE=$memc_base SIZE=$memc_size IRQ=-1" + echo " DEVID=XICU BASE=$xicu_base SIZE=$DMA_SIZE IRQ=-1" + echo " DEVID=DMA BASE=$dma_base SIZE=$XICU_SIZE IRQ=8" + echo " " + echo " " +} + +print_io_cluster() +{ + offset=$1 + cid=$2 + memc_base=$(printf "0x%X" $offset) + memc_size=$(printf "0x%X" $MEMC_SIZE) + xicu_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (XICU_TGTID << 19)))) + dma_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)))) + bdev_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (BDEV_TGTID << 19)))) + tty_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MTTY_TGTID << 19)))) + fbf_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (FBUF_TGTID << 19)))) + + echo "[CLUSTER]" + echo " CID="$cid + echo " CPU_NR="$NPROCS + echo " DEV_NR=9" + echo " DEVID=RAM BASE=$memc_base SIZE=$memc_size IRQ=-1" + echo " DEVID=XICU BASE=$xicu_base SIZE=$XICU_SIZE IRQ=-1" + echo " DEVID=DMA BASE=$dma_base SIZE=$DMA_SIZE IRQ=8" + echo " DEVID=BLKDEV BASE=$bdev_base SIZE=$BDEV_SIZE IRQ=31" + ntty=0 + irq=16 + while test $ntty -lt $NB_TTY + do + tty_base_i=$(printf "0x%X" $((tty_base + ntty * TTY_CHANNEL_SIZE))) + echo " DEVID=TTY BASE=$tty_base_i SIZE=$TTY_CHANNEL_SIZE IRQ=$irq" + irq=$((irq + 1)) + ntty=$((ntty + 1)) + done + echo " DEVID=FB BASE=$fbf_base SIZE=$FB_SIZE IRQ=-1" + echo " " + echo " " +} + +# Derive X_WIDTH form X_MAX +case $X_MAX in + 1) X_WIDTH=0 + ;; + + 2) X_WIDTH=1 + ;; + + [3-4]) X_WIDTH=2 + ;; + + [5-8]) X_WIDTH=3 + ;; + + *) X_WIDTH=4 + ;; +esac + +# Derive Y_WIDTH form Y_MAX +case $Y_MAX in + 1) Y_WIDTH=0 + ;; + + + 2) Y_WIDTH=1 + ;; + + [3-4]) Y_WIDTH=2 + ;; + + [5-8]) Y_WIDTH=3 + ;; + + *) Y_WIDTH=4 + ;; +esac + +x=0; y=0 +io_cid=$((0xbf >> (8 - X_WIDTH - Y_WIDTH))) +BSCPU=$(($io_cid * $NPROCS)) + +break_loop=0 +while test $x -lt $X_MAX +do + while test $y -lt $Y_MAX + do + cid=$((x * Y_MAX + y)) + offset=$((cid << (ADDR_WIDTH - X_WIDTH - Y_WIDTH))) + + if [ $cid -eq $io_cid ] + then + BSDMA=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)))) + BSTTY=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MTTY_TGTID << 19)))) + break_loop=1 + break + else + BSDMA="error" + fi + + y=$((y + 1)) + done + if test $break_loop -eq 1 ; then + break + fi + y=0 + x=$((x + 1)) +done + +# Generate the description +print_comments "$0" +print_header + +x=0; y=0 +while test $x -lt $X_MAX +do + while test $y -lt $Y_MAX + do + cid=$((x * Y_MAX + y)) + offset=$((cid << (ADDR_WIDTH - X_WIDTH - Y_WIDTH))) + + if [ $cid -eq $io_cid ] + then + print_io_cluster $offset $cid + else + print_cluster $offset $cid + fi + + y=$((y + 1)) + done + y=0 + x=$((x + 1)) +done + +#-------------------------------------------------------------------------# +# End of script # +#-------------------------------------------------------------------------# Index: /branches/RWT/soft/validation/scripts/run_simus.py =================================================================== --- /branches/RWT/soft/validation/scripts/run_simus.py (revision 843) +++ /branches/RWT/soft/validation/scripts/run_simus.py (revision 843) @@ -0,0 +1,393 @@ +#!/usr/bin/python + +import subprocess +import os +import sys +import shutil +import random + +# User parameters +use_omp = True +nb_procs = 4 +protocol = 'dhccp' + +nb_max_incr = 50 +nb_max_trans = 100 +nb_ml = 7 # max number of memory lines +nb_cl = 2 # max number of cache lines +cache_line_size = 16 +nb_cache_lines = 256 + +data_dir = 'data' +test_gen_tool_dir = 'TestGenerator' +test_gen_binary = 'generate_test' + +log_init_name = 'log_init_' +log_term_name = 'log_term_' +res_natif = 'res_natif.txt' + +all_protocols = [ 'dhccp', 'rwt', 'hmesi', 'wtidl' ] + +# Path +top_path = os.path.join(os.path.dirname(os.path.realpath(__file__)), "..") +config_name = os.path.join(os.path.dirname(os.path.realpath(__file__)), "config.py") + +scripts_path = os.path.join(top_path, 'scripts') +almos_path = os.path.join(top_path, 'almos') +soclib_conf_name = os.path.join(top_path, "soclib.conf") +topcell_name = os.path.join(top_path, "top.cpp") +arch_info_name = os.path.join(almos_path, "arch-info-gen.info") +arch_info_bib_name = os.path.join(almos_path, 'arch-info.bib') +hdd_img_file_name = os.path.join(almos_path, "hdd-img.bin") +shrc_file_name = os.path.join(almos_path, "shrc") +hard_config_name = os.path.join(almos_path, "hard_config.h") +app_path = os.path.join(scripts_path, 'soft') + +app_name = 'gen_test' +app_source = os.path.join(scripts_path, 'gen_test.c') + +# Checks +if protocol not in all_protocols: + help_str = ''' +*** Error: variable protocol has an unsupported value +''' + print help_str + sys.exit() + +if not os.path.isfile(config_name): + help_str = ''' +You should create a file named config.py in this directory with the following definitions: + - almos_src_dir: path to almos source directory (for kernel and bootloader binaries) + - hdd_img_name: path to the hdd image to use (will be copied but not modified) + - tsar_dir: path to tsar repository +Optional definitions (necessary if you want to use alternative protocols): + - rwt_dir: path to the RWT repository + - hmesi_dir: path to HMESI directory + - wtidl_dir: path to the ideal write-through protocol directory +*** Stopping execution +''' + print help_str + sys.exit() + +# Loading config +exec(file(config_name)) + +# Check that variables and paths exist +for var in [ 'almos_src_dir', 'hdd_img_name', 'tsar_dir' ]: + if eval(var) == "": + print "*** Error: variable %s not defined in config file" % (var) + sys.exit() + if not os.path.exists(eval(var)): + print "*** Error: variable %s does not define a valid path" % (var) + sys.exit() + +if protocol == "rwt": + if rwt_dir == "": + print "*** Error: variable rwt_dir not defined in config file" + sys.exit() + if not os.path.exists(rwt_dir): + print "*** Error: variable rwt_dir does not define a valid path" + sys.exit() + +if protocol == "hmesi": + if hmesi_dir == "": + print "*** Error: variable hmesi_dir not defined in config file" + sys.exit() + if not os.path.exists(hmesi_dir): + print "*** Error: variable hmesi_dir does not define a valid path" + sys.exit() + +if protocol == "wtidl": + if wtidl_dir == "": + print "*** Error: variable wtidl_dir not defined in config file" + sys.exit() + if not os.path.exists(wtidl_dir): + print "*** Error: variable wtidl_dir does not define a valid path" + sys.exit() + + +random.seed() + + +def get_x_y(nb_procs): + x = 1 + y = 1 + to_x = True + while (x * y * 4 < nb_procs): + if to_x: + x = x * 2 + else: + y = y * 2 + to_x = not to_x + return x, y + + +def gen_soclib_conf(): + + if os.path.isfile(soclib_conf_name): + print "Updating file %s" % (soclib_conf_name) + # First, remove lines containing "addDescPath" + f = open(soclib_conf_name, "r") + lines = f.readlines() + f.close() + + f = open(soclib_conf_name, "w") + + for line in lines: + if not ("addDescPath" in line): + f.write(line) + f.close() + else: + print "Creating file %s" % (soclib_conf_name) + f = open(soclib_conf_name, "w") + f.close() + + # Defining common and specific modules + common_modules = [ + 'lib/generic_llsc_global_table', + 'modules/dspin_router_tsar', + 'modules/sdmmc', + 'modules/vci_block_device_tsar', + 'modules/vci_ethernet_tsar', + 'modules/vci_io_bridge', + 'modules/vci_iox_network', + 'modules/vci_spi', + 'platforms/tsar_generic_xbar/tsar_xbar_cluster' + ] + + specific_modules = [ + 'communication', + 'lib/generic_cache_tsar', + 'modules/vci_cc_vcache_wrapper', + 'modules/vci_mem_cache', + ] + + f = open(soclib_conf_name, "a") + # Adding common modules + for common_module in common_modules: + f.write("config.addDescPath(\"%s/%s\")\n" % (tsar_dir, common_module)) + #f.write("\n") + + if protocol == "dhccp": + arch_dir = tsar_dir + elif protocol == "rwt": + arch_dir = rwt_dir + elif protocol == "hmesi": + arch_dir = hmesi_dir + elif protocol == "wtidl": + arch_dir = wtidl_dir + else: + assert(False) + + for specific_module in specific_modules: + f.write("config.addDescPath(\"%s/%s\")\n" % (arch_dir, specific_module)) + + #f.write("\n") + f.close() + + +def gen_hard_config(x, y, hard_config): + header = ''' +/* Generated from run_simus.py */ + +#ifndef _HD_CONFIG_H +#define _HD_CONFIG_H + +#define X_SIZE %(x)d +#define Y_SIZE %(y)d +#define NB_CLUSTERS %(nb_clus)d +#define NB_PROCS_MAX 4 +#define NB_TASKS_MAX 8 + +#define NB_TIM_CHANNELS 32 +#define NB_DMA_CHANNELS 1 + +#define NB_TTY_CHANNELS 4 +#define NB_IOC_CHANNELS 1 +#define NB_NIC_CHANNELS 0 +#define NB_CMA_CHANNELS 0 + +#define USE_XICU 1 +#define IOMMU_ACTIVE 0 + +#define IRQ_PER_PROCESSOR 1 +''' % dict(x = x, y = y, nb_clus = x * y) + + if protocol == 'wtidl': + header += '#define WT_IDL\n' + + header += '#endif //_HD_CONFIG_H\n' + + file = open(hard_config, 'w') + file.write(header) + file.close() + + + +def gen_arch_info(x, y, arch_info, arch_info_bib): + old_path = os.getcwd() + print "cd", scripts_path + os.chdir(scripts_path) + print "./gen_arch_info_large.sh", str(x), str(y), ">", arch_info + output = subprocess.Popen([ './gen_arch_info_large.sh', str(x), str(y) ], stdout = subprocess.PIPE).communicate()[0] + os.chdir(almos_path) + file = open(arch_info, 'w') + file.write(output) + file.close() + print "./info2bib -i", arch_info, "-o", arch_info_bib + subprocess.call([ './info2bib', '-i', arch_info, '-o', arch_info_bib ]) + print "cd", old_path + os.chdir(old_path) + + +def gen_sym_links(): + old_path = os.getcwd() + print "cd", almos_path + os.chdir(almos_path) + + target = os.path.join(almos_src_dir, 'tools/soclib-bootloader/bootloader-tsar-mipsel.bin') + link_name = 'bootloader-tsar-mipsel.bin' + if not os.path.isfile(link_name): + print "ln -s", target, link_name + os.symlink(target, link_name) + + target = os.path.join(almos_src_dir, 'kernel/obj.tsar/almix-tsar-mipsel.bin') + link_name = 'kernel-soclib.bin' + if not os.path.isfile(link_name): + print "ln -s", target, link_name + os.symlink(target, link_name) + + target = os.path.join(almos_src_dir, 'tools/bin/info2bib') + link_name = 'info2bib' + if not os.path.isfile(link_name): + print "ln -s", target, link_name + os.symlink(target, link_name) + + copied_hdd = 'hdd-img.bin' + print "cp", hdd_img_name, copied_hdd + shutil.copy(hdd_img_name, copied_hdd) + + + + +# Loop of simulation + +print "make -C", test_gen_tool_dir +subprocess.call([ 'make', '-C', test_gen_tool_dir ]) + +print "cp", os.path.join(test_gen_tool_dir, test_gen_binary), os.path.join(scripts_path, test_gen_binary) +subprocess.call([ 'cp', os.path.join(test_gen_tool_dir, test_gen_binary), os.path.join(scripts_path, test_gen_binary)]) + +print "mkdir -p", os.path.join(scripts_path, data_dir) +subprocess.call([ 'mkdir', '-p', os.path.join(scripts_path, data_dir) ]) + +gen_sym_links() +gen_soclib_conf() + +while True: + x, y = get_x_y(nb_procs) + nthreads = min(4, x * y) + gen_hard_config(x, y, hard_config_name) + gen_arch_info(x, y, arch_info_name, arch_info_bib_name) + + # Generating test + print test_gen_binary, nb_procs, nb_max_incr, nb_max_trans, nb_ml, nb_cl, cache_line_size, nb_cache_lines, app_source + subprocess.call([ os.path.join(scripts_path, test_gen_binary), str(nb_procs), str(nb_max_incr), str(nb_max_trans), str(nb_ml), str(nb_cl), str(cache_line_size), str(nb_cache_lines), app_source ]) + + print "cd", scripts_path + os.chdir(scripts_path) + + # Compiling and executing generated test in native + print "make -f Makefile.nat" + subprocess.call([ 'make', '-f', 'Makefile.nat' ]) + + print "./test_natif >", os.path.join(data_dir, res_natif) + output = subprocess.Popen([ './test_natif' ], stdout = subprocess.PIPE).communicate()[0] + file = open(os.path.join(data_dir, res_natif), 'w') + file.write(output) + file.close() + + # Building simulated soft + print "cp", app_source, app_path + subprocess.call([ 'cp', app_source, app_path ]) + + old_path = os.getcwd() + print "cd", app_path + os.chdir(app_path) + + # Compilation process is different in splash and other apps + print "make clean" + subprocess.call([ 'make', 'clean' ]) + + print "make TARGET=tsar" + subprocess.call([ 'make', 'TARGET=tsar' ]) + + # Creation/Modification du shrc de almos + shrc = "exec -p 0 /bin/gen_test\n" + + file = open(shrc_file_name, 'w') + file.write(shrc) + file.close() + + # Copie du binaire et du shrc dans l'image disque + print "mcopy -o -i", hdd_img_file_name, shrc_file_name, "::/etc/" + subprocess.call([ 'mcopy', '-o', '-i', hdd_img_file_name, shrc_file_name, '::/etc/' ]) + print "mcopy -o -i", hdd_img_file_name, app_name, "::/bin/" + subprocess.call([ 'mcopy', '-o', '-i', hdd_img_file_name, app_name, '::/bin/' ]) + + print "cd", old_path + os.chdir(old_path) + + # Compiling topcell + print "cd", top_path + os.chdir(top_path) + print "touch", topcell_name + subprocess.call([ 'touch', topcell_name ]) + print "make" + retval = subprocess.call([ 'make' ]) + if retval != 0: + sys.exit() + + # Launching simulation + if use_omp: + print "./simul.x -THREADS", nthreads, ">", os.path.join(scripts_path, data_dir, log_init_name + str(nb_procs)) + output = subprocess.Popen([ './simul.x', '-THREADS', str(nthreads) ], stdout = subprocess.PIPE).communicate()[0] + else: + print "./simul.x >" , os.path.join(scripts_path, data_dir, log_init_name + str(nb_procs)) + output = subprocess.Popen([ './simul.x' ], stdout = subprocess.PIPE).communicate()[0] + + # Writing simulation results to data directory + print "cd", scripts_path + os.chdir(scripts_path) + filename = os.path.join(data_dir, log_init_name + str(nb_procs)) + file = open(filename, 'w') + file.write(output) + file.close() + + term_filename = os.path.join(scripts_path, data_dir, log_term_name + str(nb_procs)) + print "tail -n +5", os.path.join(top_path, 'term1'), ">", term_filename + output = subprocess.Popen([ 'tail', '-n', '+5', os.path.join(top_path, 'term1') ], stdout = subprocess.PIPE).communicate()[0] + file = open(term_filename, 'w') + file.write(output) + file.close() + + # Quiting if results obtained by simulation are incorrect + print "diff", term_filename, os.path.join(data_dir, res_natif) + output = subprocess.Popen([ 'diff', term_filename, os.path.join(data_dir, res_natif) ], stdout = subprocess.PIPE).communicate()[0] + if output != "": + print "*** Difference found, stopping" + break; + else: + print "No diff found, continuing" + + +## Enf of simulations + + + + + + + + + Index: /branches/RWT/soft/validation/scripts/soft/Makefile =================================================================== --- /branches/RWT/soft/validation/scripts/soft/Makefile (revision 843) +++ /branches/RWT/soft/validation/scripts/soft/Makefile (revision 843) @@ -0,0 +1,8 @@ + +FILES = gen_test +BIN = gen_test + +ADD-LDFLAGS = -lpthread + +include $(ALMOS_TOP)/sys/mk/include/appli.mk + Index: /branches/RWT/soft/validation/top.cpp =================================================================== --- /branches/RWT/soft/validation/top.cpp (revision 843) +++ /branches/RWT/soft/validation/top.cpp (revision 843) @@ -0,0 +1,1175 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : may 2013 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture. +// The physical address space is 40 bits. +// +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 8. +// +// - It uses four dspin_local_crossbar per cluster as local interconnect +// - It uses two virtual_dspin routers per cluster as global interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains one vci_xicu per cluster. +// - It contains one vci_multi_dma per cluster. +// - It contains one vci_simple_ram per cluster to model the L3 cache. +// +// The communication between the MemCache and the Xram is 64 bits. +// +// All clusters are identical, but the cluster 0 (called io_cluster), +// contains 6 extra components: +// - the boot rom (BROM) +// - the disk controller (BDEV) +// - the multi-channel network controller (MNIC) +// - the multi-channel chained buffer dma controller (CDMA) +// - the multi-channel tty controller (MTTY) +// - the frame buffer controller (FBUF) +// +// It is build with one single component implementing a cluster, +// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) +// +// The IRQs are connected to XICUs as follow: +// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. +// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. +// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. +// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. +// +// Some hardware parameters are used when compiling the OS, and are used +// by this top.cpp file. They must be defined in the hard_config.h file : +// - CLUSTER_X : number of clusters in a row (power of 2) +// - CLUSTER_Y : number of clusters in a column (power of 2) +// - CLUSTER_SIZE : size of the segment allocated to a cluster +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) +// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) +// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) +// +// Some other hardware parameters are not used when compiling the OS, +// and can be directly defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_SECTOR_SIZE : block size for block drvice +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container +///////////////////////////////////////////////////////////////////////// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 24 | +///////////////////////////////////////////////////////////////////////// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// | X_ID | Y_ID |---| L_ID | +// |x_width|y_width|---| 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "alloc_elems.h" +#include "tsar_xbar_cluster.h" + +#define USE_ALMOS 1 +//#define USE_GIET + +#ifdef USE_ALMOS +#ifdef USE_GIET +#error "Can't use Two different OS" +#endif +#endif + +#ifndef USE_ALMOS +#ifndef USE_GIET +#error "You need to specify one OS" +#endif +#endif + +#ifdef USE_ALMOS + #define PREFIX_OS "almos/" + #include "almos/hard_config.h" +#endif +#ifdef USE_GIET + #define PREFIX_OS "giet_vm/" +#endif + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// + + +#if USE_OPENMP +#include +#endif + +// cluster index (computed from x,y coordinates) +#ifdef USE_ALMOS + #define cluster(x,y) (y + x * Y_SIZE) +#else + #define cluster(x,y) (y + (x << Y_WIDTH)) +#endif + + +#define min(x, y) (x < y ? x : y) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 + +#ifdef USE_ALMOS +#define vci_address_width 32 +#endif +#ifdef USE_GIET +#define vci_address_width 40 +#endif +#define vci_plen_width 8 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters +//////////////////////i///////////////////////////////////// + + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#ifdef USE_ALMOS +#define FBUF_X_SIZE 1024 +#define FBUF_Y_SIZE 1024 +#endif +#ifdef USE_GIET +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 +#endif + +#ifdef USE_GIET +#define BDEV_SECTOR_SIZE 512 +#define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw" +#endif +#ifdef USE_ALMOS +#define BDEV_SECTOR_SIZE 4096 +#define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin" +#endif + +#define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt" +#define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt" +#define NIC_TIMEOUT 10000 + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM & RAM +//////////////////////i///////////////////////////////////// + +#ifdef USE_ALMOS +#define soft_name PREFIX_OS"bootloader-tsar-mipsel.bin",\ + PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\ + PREFIX_OS"arch-info.bib@0xBFC08000:D" +#endif +#ifdef USE_GIET +#define soft_pathname PREFIX_OS"soft.elf" +#endif + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// + +#define MAX_FROZEN_CYCLES 100000000 + + +//////////////////////////////////////////////////////////////////// +// TGTID definition in direct space +// For all components: global TGTID = global SRCID = cluster_index +//////////////////////////////////////////////////////////////////// + +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define MDMA_TGTID 2 +#define MTTY_TGTID 3 +#define BDEV_TGTID 4 +#define MNIC_TGTID 5 +#define BROM_TGTID 6 +#define CDMA_TGTID 7 +#define SIMH_TGTID 8 +#define FBUF_TGTID 9 + + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// +// There is 3 segments replicated in all clusters +// and 5 specific segments in the "IO" cluster +// (containing address 0xBF000000) +///////////////////////////////////////////////////////// + +#ifdef USE_GIET + // specific segments in "IO" cluster : absolute physical address + #define BROM_BASE 0x00BFC00000 + #define BROM_SIZE 0x0000100000 // 1 Mbytes + + #define FBUF_BASE 0x00B2000000 + #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) + + #define BDEV_BASE 0x00B3000000 + #define BDEV_SIZE 0x0000001000 // 4 Kbytes + + #define MTTY_BASE 0x00B4000000 + #define MTTY_SIZE 0x0000001000 // 4 Kbytes + + #define MNIC_BASE 0x00B5000000 + #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels) + + #define CDMA_BASE 0x00B6000000 + #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS + + // replicated segments : address is incremented by a cluster offset + // offset = cluster(x,y) << (address_width-x_width-y_width); + + #define MEMC_BASE 0x0000000000 + #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster + + #define XICU_BASE 0x00B0000000 + #define XICU_SIZE 0x0000001000 // 4 Kbytes + + #define MDMA_BASE 0x00B1000000 + #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel + + #define SIMH_BASE 0x00B7000000 + #define SIMH_SIZE 0x0000001000 +#endif + +#ifdef USE_ALMOS + // 2^19 is the offset for the local id (8 bits for global ID : + // 1 bit for Memcache or Peripheral, 4 for local peripheral id) + // (Almos supports 32 bits physical addresses) + + #define CLUSTER_INC (0x80000000ULL / (X_SIZE * Y_SIZE) * 2) + + #define CLUSTER_IO_INC (cluster_io_id * CLUSTER_INC) + #define MEMC_MAX_SIZE (0x40000000 / (X_SIZE * Y_SIZE)) // 0x40000000 : valeur totale souhaitée (ici : 1Go) + + #define BROM_BASE 0x00BFC00000 + #define BROM_SIZE 0x0000100000 // 1 Mbytes + + #define MEMC_BASE 0x0000000000 + #define MEMC_SIZE min(0x04000000, MEMC_MAX_SIZE) + + #define XICU_BASE (CLUSTER_INC >> 1) + (XICU_TGTID << 19) + #define XICU_SIZE 0x0000001000 // 4 Kbytes + + #define MDMA_BASE (CLUSTER_INC >> 1) + (MDMA_TGTID << 19) + #define MDMA_SIZE (0x0000001000 * NB_DMA_CHANNELS) // 4 Kbytes per channel + + #define BDEV_BASE (CLUSTER_INC >> 1) + (BDEV_TGTID << 19) + (CLUSTER_IO_INC) + #define BDEV_SIZE 0x0000001000 // 4 Kbytes + + #define MTTY_BASE (CLUSTER_INC >> 1) + (MTTY_TGTID << 19) + (CLUSTER_IO_INC) + #define MTTY_SIZE 0x0000001000 // 4 Kbytes + + #define FBUF_BASE (CLUSTER_INC >> 1) + (FBUF_TGTID << 19) + (CLUSTER_IO_INC) + #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000 + + #define MNIC_BASE (CLUSTER_INC >> 1) + (MNIC_TGTID << 19) + (CLUSTER_IO_INC) + #define MNIC_SIZE 0x0000080000 + + #define CDMA_BASE (CLUSTER_INC >> 1) + (CDMA_TGTID << 19) + (CLUSTER_IO_INC) + #define CDMA_SIZE (0x0000004000 * NB_CMA_CHANNELS) + + #define SIMH_BASE (CLUSTER_INC >> 1) + (SIMH_TGTID << 19) + (CLUSTER_IO_INC) + #define SIMH_SIZE 0x0000001000 +#endif + +bool stop_called = false; + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + +#ifdef USE_GIET + char soft_name[256] = soft_pathname; // pathname to binary code +#endif + const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call + int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0; // index of memc to be traced + size_t debug_proc_id = 0; // index of proc to be traced + int64_t debug_from = 0; // trace start cycle + int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_io_id; // index of cluster containing IOs + int64_t reset_counters = -1; + int64_t dump_counters = -1; + bool do_reset_counters = false; + bool do_dump_counters = false; + struct timeval t1, t2; + uint64_t ms1, ms2; + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) + { + ncycles = (int64_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) + { +#ifdef USE_ALMOS + assert( 0 && "Can't define almos soft name" ); +#endif +#ifdef USE_GIET + strcpy(soft_name, argv[n + 1]); +#endif + } + else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) + { + strcpy(disk_name, argv[n + 1]); + } + else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) + { + debug_ok = true; + debug_from = (int64_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) + { + debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); +#ifdef USE_ALMOS + assert((debug_memc_id < (X_SIZE * Y_SIZE)) && + "debug_memc_id larger than X_SIZE * Y_SIZE" ); +#else + size_t x = debug_memc_id >> Y_WIDTH; + size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); + + assert( (x <= X_SIZE) and (y <= Y_SIZE) && + "MEMCID parameter refers a not valid memory cache"); +#endif + } + else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) + { + debug_proc_id = (size_t) strtol(argv[n + 1], NULL, 0); +#ifdef USE_ALMOS + assert((debug_proc_id < (X_SIZE * Y_SIZE * NB_PROCS_MAX)) && + "debug_proc_id larger than X_SIZE * Y_SIZE * NB_PROCS"); +#else + size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; + size_t x = cluster_xy >> Y_WIDTH; + size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); + + assert( (x <= X_SIZE) and (y <= Y_SIZE) && + "PROCID parameter refers a not valid processor"); +#endif + } + else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) + { + threads_nr = (ssize_t) strtol(argv[n + 1], NULL, 0); + threads_nr = (threads_nr < 1) ? 1 : threads_nr; + } + else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) + { + frozen_cycles = (int64_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) + { + debug_period = (size_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n], "--reset-counters") == 0) && (n + 1 < argc)) + { + reset_counters = (int64_t) strtol(argv[n + 1], NULL, 0); + do_reset_counters = true; + } + else if ((strcmp(argv[n], "--dump-counters") == 0) && (n + 1 < argc)) + { + dump_counters = (int64_t) strtol(argv[n + 1], NULL, 0); + do_dump_counters = true; + } + else + { + std::cout << " Arguments are (key,value) couples." << std::endl; + std::cout << " The order is not important." << std::endl; + std::cout << " Accepted arguments are :" << std::endl << std::endl; + std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; + std::cout << " -DISK pathname_for_disk_image" << std::endl; + std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; + std::cout << " -DEBUG debug_start_cycle" << std::endl; + std::cout << " -THREADS simulator's threads number" << std::endl; + std::cout << " -FROZEN max_number_of_lines" << std::endl; + std::cout << " -PERIOD number_of_cycles between trace" << std::endl; + std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; + std::cout << " -PROCID index_proc_to_be_traced" << std::endl; + exit(0); + } + } + } + + // checking hardware parameters + assert( ( (X_SIZE == 1) or (X_SIZE == 2) or (X_SIZE == 4) or + (X_SIZE == 8) or (X_SIZE == 16) ) and + "The X_SIZE parameter must be 1, 2, 4, 8 or 16" ); + + assert( ( (Y_SIZE == 1) or (Y_SIZE == 2) or (Y_SIZE == 4) or + (Y_SIZE == 8) or (Y_SIZE == 16) ) and + "The Y_SIZE parameter must be 1, 2, 4, 8 or 16" ); + + assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or + (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and + "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); + + assert( (NB_DMA_CHANNELS < 9) and + "The NB_DMA_CHANNELS parameter must be smaller than 9" ); + + assert( (NB_TTY_CHANNELS < 15) and + "The NB_TTY_CHANNELS parameter must be smaller than 15" ); + + assert( (NB_NIC_CHANNELS < 9) and + "The NB_NIC_CHANNELS parameter must be smaller than 9" ); + +#ifdef USE_GIET + assert( (vci_address_width == 40) and + "VCI address width with the GIET must be 40 bits" ); +#endif + +#ifdef USE_ALMOS + assert( (vci_address_width == 32) and + "VCI address width with ALMOS must be 32 bits" ); +#endif + + + std::cout << std::endl; + std::cout << " - X_SIZE = " << X_SIZE << std::endl; + std::cout << " - Y_SIZE = " << Y_SIZE << std::endl; + std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; + std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; + std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; + std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; + std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; + std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; + std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; + std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; + + std::cout << std::endl; + // Internal and External VCI parameters definition + typedef soclib::caba::VciParams vci_param_int; + + typedef soclib::caba::VciParams vci_param_ext; + +#if USE_OPENMP + omp_set_dynamic(false); + omp_set_num_threads(threads_nr); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + + // Define parameters depending on mesh size + size_t x_width; + size_t y_width; + +#ifdef USE_ALMOS + if (X_SIZE == 1) x_width = 0; + else if (X_SIZE == 2) x_width = 1; + else if (X_SIZE <= 4) x_width = 2; + else if (X_SIZE <= 8) x_width = 3; + else x_width = 4; + + if (Y_SIZE == 1) y_width = 0; + else if (Y_SIZE == 2) y_width = 1; + else if (Y_SIZE <= 4) y_width = 2; + else if (Y_SIZE <= 8) y_width = 3; + else y_width = 4; + +#else + size_t x_width = X_WIDTH; + size_t y_width = Y_WIDTH; + + assert( (X_WIDTH <= 4) and (Y_WIDTH <= 4) and + "Up to 256 clusters"); + + assert( (X_SIZE <= (1 << X_WIDTH)) and (Y_SIZE <= (1 << Y_WIDTH)) and + "The X_WIDTH and Y_WIDTH parameter are insufficient"); + +#endif + + // index of cluster containing IOs + cluster_io_id = 0x00bfc00000ULL >> (vci_address_width - x_width - y_width); + + + ///////////////////// + // Mapping Tables + ///////////////////// + + // internal network + MappingTable maptabd(vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FF800000); + + for (size_t x = 0; x < X_SIZE; x++) + { + for (size_t y = 0; y < Y_SIZE; y++) + { + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream si; + si << "seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE, + IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE, + IntTab(cluster(x,y),MDMA_TGTID), false)); + + std::ostringstream sh; + sh << "seg_memc_" << x << "_" << y; + maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), true)); + + if ( cluster(x,y) == cluster_io_id ) + { + maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, + IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, + IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, + IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, + IntTab(cluster(x,y),BROM_TGTID), true)); + maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, + IntTab(cluster(x,y),MNIC_TGTID), false)); + maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE, + IntTab(cluster(x,y),CDMA_TGTID), false)); + maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE, + IntTab(cluster(x,y),SIMH_TGTID), false)); + } + } + } + std::cout << maptabd << std::endl; + + // external network + MappingTable maptabx(vci_address_width, + IntTab(x_width+y_width), + IntTab(x_width+y_width), + 0xFFFF000000ULL); + + for (size_t x = 0; x < X_SIZE; x++) + { + for (size_t y = 0; y < Y_SIZE ; y++) + { + + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width - x_width - y_width); + + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + + maptabx.add(Segment(sh.str(), MEMC_BASE + offset, + MEMC_SIZE, IntTab(cluster(x,y)), false)); + } + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + // Horizontal inter-clusters DSPIN signals + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE, 3); + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE, 3); + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE, 2); + + // Vertical inter-clusters DSPIN signals + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1, 3); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1, 3); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1, 2); + + // Mesh boundaries DSPIN signals + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in" , X_SIZE, Y_SIZE, 4, 3); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", X_SIZE, Y_SIZE, 4, 3); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in" , X_SIZE, Y_SIZE, 4, 2); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", X_SIZE, Y_SIZE, 4, 2); + + //////////////////////////// + // Loader + //////////////////////////// + + soclib::common::Loader loader(soft_name); + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////// + // Clusters construction + //////////////////////////// + + TsarXbarCluster * clusters[X_SIZE][Y_SIZE]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) + { + size_t x = i / Y_SIZE; + size_t y = i % Y_SIZE; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << x << "_" << y << std::endl; + std::cout << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarXbarCluster + ( + sc.str().c_str(), + NB_PROCS_MAX, + NB_TTY_CHANNELS, + NB_DMA_CHANNELS, + x, + y, + cluster(x,y), + maptabd, + maptabx, + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + CDMA_TGTID, + BDEV_TGTID, + SIMH_TGTID, + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + IRQ_PER_PROCESSOR, + XRAM_LATENCY, + (cluster(x,y) == cluster_io_id), + FBUF_X_SIZE, + FBUF_Y_SIZE, + disk_name, + BDEV_SECTOR_SIZE, + NB_NIC_CHANNELS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + NB_CMA_CHANNELS, + loader, + frozen_cycles, + debug_from, + debug_ok, + debug_ok + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // Clock & RESET + for (size_t x = 0; x < (X_SIZE); x++){ + for (size_t y = 0; y < Y_SIZE; y++){ + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (X_SIZE > 1){ + for (size_t x = 0; x < (X_SIZE-1); x++){ + for (size_t y = 0; y < Y_SIZE; y++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); + clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); + } + } + } + } + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (Y_SIZE > 1) { + for (size_t y = 0; y < (Y_SIZE-1); y++){ + for (size_t x = 0; x < X_SIZE; x++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < Y_SIZE; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in [0][y][WEST][k]); + clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); + clusters[X_SIZE-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in [X_SIZE-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_cmd_out[EAST][k](signal_dspin_false_cmd_out[X_SIZE-1][y][EAST][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in [0][y][WEST][k]); + clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); + clusters[X_SIZE-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in [X_SIZE-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_rsp_out[EAST][k](signal_dspin_false_rsp_out[X_SIZE-1][y][EAST][k]); + } + } + + // North & South boundary clusters connections + for (size_t x = 0; x < X_SIZE; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in [x][0][SOUTH][k]); + clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); + clusters[x][Y_SIZE-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in [x][Y_SIZE-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_cmd_out[NORTH][k](signal_dspin_false_cmd_out[x][Y_SIZE-1][NORTH][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in [x][0][SOUTH][k]); + clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); + clusters[x][Y_SIZE-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in [x][Y_SIZE-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_rsp_out[NORTH][k](signal_dspin_false_rsp_out[x][Y_SIZE-1][NORTH][k]); + } + } + std::cout << "North, South, West, East connections established" << std::endl; + std::cout << std::endl; + + +#ifdef WT_IDL + std::list > * > l1_caches; + + for (size_t x = 0; x < X_SIZE; x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + for (int proc = 0; proc < NB_PROCS_MAX; proc++) { + l1_caches.push_back(clusters[x][y]->proc[proc]); + } + } + } + + for (size_t x = 0; x < X_SIZE; x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->set_vcache_list(l1_caches); + } + } +#endif + + +//#define SC_TRACE +#ifdef SC_TRACE + sc_trace_file * tf = sc_create_vcd_trace_file("my_trace_file"); + + if (X_SIZE > 1){ + for (size_t x = 0; x < (X_SIZE-1); x++){ + for (size_t y = 0; y < Y_SIZE; y++){ + for (size_t k = 0; k < 3; k++){ + signal_dspin_h_cmd_inc[x][y][k].trace(tf, "dspin_h_cmd_inc"); + signal_dspin_h_cmd_dec[x][y][k].trace(tf, "dspin_h_cmd_dec"); + } + + for (size_t k = 0; k < 2; k++){ + signal_dspin_h_rsp_inc[x][y][k].trace(tf, "dspin_h_rsp_inc"); + signal_dspin_h_rsp_dec[x][y][k].trace(tf, "dspin_h_rsp_dec"); + } + } + } + } + + if (Y_SIZE > 1) { + for (size_t y = 0; y < (Y_SIZE-1); y++){ + for (size_t x = 0; x < X_SIZE; x++){ + for (size_t k = 0; k < 3; k++){ + signal_dspin_v_cmd_inc[x][y][k].trace(tf, "dspin_v_cmd_inc"); + signal_dspin_v_cmd_dec[x][y][k].trace(tf, "dspin_v_cmd_dec"); + } + + for (size_t k = 0; k < 2; k++){ + signal_dspin_v_rsp_inc[x][y][k].trace(tf, "dspin_v_rsp_inc"); + signal_dspin_v_rsp_dec[x][y][k].trace(tf, "dspin_v_rsp_dec"); + } + } + } + } + + for (size_t x = 0; x < (X_SIZE); x++){ + for (size_t y = 0; y < Y_SIZE; y++){ + std::ostringstream signame; + signame << "cluster" << x << "_" << y; + clusters[x][y]->trace(tf, signame.str()); + } + } +#endif + + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for (size_t x = 0; x < X_SIZE ; x++){ + for (size_t y = 0; y < Y_SIZE ; y++){ + for (size_t a = 0; a < 4; a++){ + for (size_t k = 0; k < 3; k++){ + signal_dspin_false_cmd_in [x][y][a][k].write = false; + signal_dspin_false_cmd_in [x][y][a][k].read = true; + signal_dspin_false_cmd_out[x][y][a][k].write = false; + signal_dspin_false_cmd_out[x][y][a][k].read = true; + } + for (size_t k = 0; k < 2; k++){ + signal_dspin_false_rsp_in [x][y][a][k].write = false; + signal_dspin_false_rsp_in [x][y][a][k].read = true; + signal_dspin_false_rsp_out[x][y][a][k].write = false; + signal_dspin_false_rsp_out[x][y][a][k].read = true; + } + } + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + if (debug_ok) { + #if USE_OPENMP + assert(false && "OPEN MP should not be used with debug because of its traces"); + #endif + + if (gettimeofday(&t1, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + for (int64_t n = 1; n < ncycles && !stop_called; n++) + { + if ((n % max_cycles) == 0) + { + + if (gettimeofday(&t2, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; + ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; + std::cerr << "platform clock frequency " << (double) max_cycles / (double) (ms2 - ms1) << "Khz" << std::endl; + + if (gettimeofday(&t1, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + } + + + if (n == reset_counters) { + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->reset_counters(); + } + } + } + + if (n == dump_counters) { + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->print_stats(true, false); + } + } + } + + if ((n > debug_from) and (n % debug_period == 0)) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << "************************************************" << std::endl; + + for (size_t x = 0; x < X_SIZE ; x++){ + for (size_t y = 0; y < Y_SIZE ; y++){ + for (int proc = 0; proc < NB_PROCS_MAX; proc++) { + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc ; + std::ostringstream p2m_signame; + p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " P2M"; + std::ostringstream m2p_signame; + m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " M2P"; + + clusters[x][y]->signal_vci_ini_proc[proc].print_trace(proc_signame.str()); + clusters[x][y]->signal_dspin_p2m_proc[proc].print_trace(p2m_signame.str()); + clusters[x][y]->signal_dspin_m2p_proc[proc].print_trace(m2p_signame.str()); + clusters[x][y]->proc[proc]->print_trace(); + } + std::ostringstream smemc; + smemc << "[SIG]MEMC_" << x << "_" << y; + std::ostringstream sxram; + sxram << "[SIG]XRAM_" << x << "_" << y; + std::ostringstream sm2p; + sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P"; + std::ostringstream sp2m; + sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M"; + + clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); + clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); + clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); + clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); + clusters[x][y]->memc->print_trace(); + } + } + } + sc_start(sc_core::sc_time(1, SC_NS)); + } + } + else { + int64_t n = 0; + while (!stop_called && n != ncycles) { + if (gettimeofday(&t1, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + int64_t nb_cycles = min(max_cycles, ncycles - n); + if (do_reset_counters) { + nb_cycles = min(nb_cycles, reset_counters - n); + } + if (do_dump_counters) { + nb_cycles = min(nb_cycles, dump_counters - n); + } + + sc_start(sc_core::sc_time(nb_cycles, SC_NS)); + n += nb_cycles; + + if (do_reset_counters && n == reset_counters) { + // Reseting counters + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->reset_counters(); + } + } + do_reset_counters = false; + } + + if (do_dump_counters && n == dump_counters) { + // Dumping counters + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->print_stats(true, false); + } + } + do_dump_counters = false; + } + + + if (gettimeofday(&t2, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; + ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; + std::cerr << std::dec << "cycle " << n << " platform clock frequency " << (double) nb_cycles / (double) (ms2 - ms1) << "Khz" << std::endl; + } + } + + + // Free memory + for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) + { + size_t x = i / Y_SIZE; + size_t y = i % Y_SIZE; + delete clusters[x][y]; + } + + dealloc_elems >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE, 3); + dealloc_elems >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE, 3); + dealloc_elems >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE, 2); + dealloc_elems >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE, 2); + dealloc_elems >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1, 3); + dealloc_elems >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1, 3); + dealloc_elems >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1, 2); + dealloc_elems >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1, 2); + dealloc_elems >(signal_dspin_false_cmd_in, X_SIZE, Y_SIZE, 4, 3); + dealloc_elems >(signal_dspin_false_cmd_out, X_SIZE, Y_SIZE, 4, 3); + dealloc_elems >(signal_dspin_false_rsp_in, X_SIZE, Y_SIZE, 4, 2); + dealloc_elems >(signal_dspin_false_rsp_out, X_SIZE, Y_SIZE, 4, 2); + + return EXIT_SUCCESS; +} + + +void handler(int dummy = 0) { + stop_called = true; + sc_stop(); +} + +void voidhandler(int dummy = 0) {} + +int sc_main (int argc, char *argv[]) +{ + signal(SIGINT, handler); + signal(SIGPIPE, voidhandler); + + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 Index: /branches/RWT/soft/validation/top.desc =================================================================== --- /branches/RWT/soft/validation/top.desc (revision 843) +++ /branches/RWT/soft/validation/top.desc (revision 843) @@ -0,0 +1,46 @@ + +# -*- python -*- + +# internal VCI parameters values +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 32 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 + +todo = Platform('caba', 'top.cpp', + + uses = [ + Uses('caba:tsar_xbar_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, +)