Index: /branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- /branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 844) +++ /branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 845) @@ -266,4 +266,5 @@ MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access + MMU_READ_DATA_TIMEOUT = 0x1200, // Read & Watchdog timeout }; @@ -433,6 +434,6 @@ // communication between DCACHE FSM and VCI_CMD FSM - sc_signal r_dcache_vci_paddr; // physical address for VCI command - sc_signal r_dcache_vci_wdata; // write unc data for VCI command + sc_signal r_dcache_vci_paddr; // physical address for VCI command + sc_signal r_dcache_vci_wdata; // write unc data for VCI command sc_signal r_dcache_vci_miss_req; // read miss request sc_signal r_dcache_vci_unc_req; // uncacheable request (read/write) @@ -447,43 +448,47 @@ // register used for XTN inval - sc_signal r_dcache_xtn_way; // selected way (from dcache) - sc_signal r_dcache_xtn_set; // selected set (from dcache) + sc_signal r_dcache_xtn_way; // selected way (from dcache) + sc_signal r_dcache_xtn_set; // selected set (from dcache) // handling dcache miss - sc_signal r_dcache_miss_type; // depending on the requester - sc_signal r_dcache_miss_word; // word index for cache update - sc_signal r_dcache_miss_way; // selected way for cache update - sc_signal r_dcache_miss_set; // selected set for cache update + sc_signal r_dcache_miss_type; // depending on the requester + sc_signal r_dcache_miss_word; // word index for cache update + sc_signal r_dcache_miss_way; // selected way for cache update + sc_signal r_dcache_miss_set; // selected set for cache update sc_signal r_dcache_miss_inval; // coherence request matching a miss sc_signal r_dcache_miss_clack; // waiting for a cleanup acknowledge + + // Watchdog timer (WDT) for MISS timeout exception (black-hole detection) + sc_signal r_dcache_miss_wdt_max; // wdt triggering value + sc_signal r_dcache_miss_wdt; // wdt counter // handling coherence requests sc_signal r_dcache_cc_way; // selected way for cc update/inval sc_signal r_dcache_cc_set; // selected set for cc update/inval - sc_signal r_dcache_cc_word; // word counter for cc update + sc_signal r_dcache_cc_word; // word counter for cc update sc_signal r_dcache_cc_need_write; // activate the cache for writing // coherence clack handling sc_signal r_dcache_clack_req; // clack request - sc_signal r_dcache_clack_way; // clack way - sc_signal r_dcache_clack_set; // clack set + sc_signal r_dcache_clack_way; // clack way + sc_signal r_dcache_clack_set; // clack set // dcache flush handling - sc_signal r_dcache_flush_count; // slot counter used for cache flush + sc_signal r_dcache_flush_count; // slot counter used for cache flush // ll response handling - sc_signal r_dcache_ll_rsp_count; // flit counter used for ll rsp + sc_signal r_dcache_ll_rsp_count; // flit counter used for ll rsp // used by the TLB miss sub-fsm - sc_signal r_dcache_tlb_vaddr; // virtual address for a tlb miss - sc_signal r_dcache_tlb_ins; // target tlb (itlb if true) - sc_signal r_dcache_tlb_paddr; // physical address of pte - sc_signal r_dcache_tlb_pte_flags; // pte1 or first word of pte2 - sc_signal r_dcache_tlb_pte_ppn; // second word of pte2 - sc_signal r_dcache_tlb_cache_way; // selected way in dcache - sc_signal r_dcache_tlb_cache_set; // selected set in dcache + sc_signal r_dcache_tlb_vaddr; // virtual address for a tlb miss + sc_signal r_dcache_tlb_ins; // target tlb (itlb if true) + sc_signal r_dcache_tlb_paddr; // physical address of pte + sc_signal r_dcache_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_dcache_tlb_pte_ppn; // second word of pte2 + sc_signal r_dcache_tlb_cache_way; // selected way in dcache + sc_signal r_dcache_tlb_cache_set; // selected set in dcache sc_signal r_dcache_tlb_cache_word; // selected word in dcache - sc_signal r_dcache_tlb_way; // selected way in tlb - sc_signal r_dcache_tlb_set; // selected set in tlb + sc_signal r_dcache_tlb_way; // selected way in tlb + sc_signal r_dcache_tlb_set; // selected set in tlb // ITLB and DTLB invalidation @@ -519,6 +524,6 @@ sc_signal r_vci_cmd_min; // used for write bursts sc_signal r_vci_cmd_max; // used for write bursts - sc_signal r_vci_cmd_cpt; // used for write bursts - sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss + sc_signal r_vci_cmd_cpt; // used for write bursts + sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss /////////////////////////////////// @@ -529,6 +534,6 @@ sc_signal r_vci_rsp_ins_error; sc_signal r_vci_rsp_data_error; - GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM - GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM + GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM + GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM /////////////////////////////////// @@ -551,17 +556,17 @@ // communication between CC_RECEIVE FSM and ICACHE FSM - sc_signal r_cc_receive_icache_req; // cc_receive to icache request - sc_signal r_cc_receive_icache_type; // cc_receive type of request - sc_signal r_cc_receive_icache_way; // cc_receive to icache way - sc_signal r_cc_receive_icache_set; // cc_receive to icache set - sc_signal r_cc_receive_icache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_icache_req; // cc_receive to icache request + sc_signal r_cc_receive_icache_type; // cc_receive type of request + sc_signal r_cc_receive_icache_way; // cc_receive to icache way + sc_signal r_cc_receive_icache_set; // cc_receive to icache set + sc_signal r_cc_receive_icache_updt_tab_idx; // cc_receive update table index sc_signal r_cc_receive_icache_nline; // cache line physical address // communication between CC_RECEIVE FSM and DCACHE FSM - sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request - sc_signal r_cc_receive_dcache_type; // cc_receive type of request - sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way - sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set - sc_signal r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request + sc_signal r_cc_receive_dcache_type; // cc_receive type of request + sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way + sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set + sc_signal r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index sc_signal r_cc_receive_dcache_nline; // cache line physical address Index: /branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 844) +++ /branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 845) @@ -331,4 +331,6 @@ r_dcache_miss_set("r_dcache_miss_set"), r_dcache_miss_inval("r_dcache_miss_inval"), + r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"), + r_dcache_miss_wdt("r_dcache_miss_wdt"), r_dcache_cc_way("r_dcache_cc_way"), @@ -811,4 +813,7 @@ r_dcache_clack_req = false; + + // Reset watchdog timer threshold to max value + r_dcache_miss_wdt_max = UINT32_MAX; // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs @@ -4142,4 +4147,7 @@ r_dcache_miss_set = set; + // reset to 0 the miss watchdog timer + r_dcache_miss_wdt = 0; + if (cleanup) { @@ -4265,4 +4273,15 @@ r_dcache_fsm = DCACHE_CC_CHECK; r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // increment MISS watchdog timer for black-hole detection + r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1; + if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) { + r_mmu_detr = MMU_READ_DATA_TIMEOUT; + r_mmu_dbvar = r_dcache_save_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + r_dcache_fsm = DCACHE_IDLE; break; }