- Timestamp:
- Oct 16, 2014, 10:57:42 AM (10 years ago)
- File:
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- 1 edited
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branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r840 r845 266 266 MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 267 267 MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access 268 MMU_READ_DATA_TIMEOUT = 0x1200, // Read & Watchdog timeout 268 269 }; 269 270 … … 433 434 434 435 // communication between DCACHE FSM and VCI_CMD FSM 435 sc_signal<paddr_t> r_dcache_vci_paddr; 436 sc_signal<uint32_t> r_dcache_vci_wdata; 436 sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command 437 sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command 437 438 sc_signal<bool> r_dcache_vci_miss_req; // read miss request 438 439 sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) … … 447 448 448 449 // register used for XTN inval 449 sc_signal<size_t> r_dcache_xtn_way; 450 sc_signal<size_t> r_dcache_xtn_set; 450 sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) 451 sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) 451 452 452 453 // handling dcache miss 453 sc_signal<int> r_dcache_miss_type;// depending on the requester454 sc_signal<size_t> r_dcache_miss_word; 455 sc_signal<size_t> r_dcache_miss_way; 456 sc_signal<size_t> r_dcache_miss_set; 454 sc_signal<int> r_dcache_miss_type; // depending on the requester 455 sc_signal<size_t> r_dcache_miss_word; // word index for cache update 456 sc_signal<size_t> r_dcache_miss_way; // selected way for cache update 457 sc_signal<size_t> r_dcache_miss_set; // selected set for cache update 457 458 sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss 458 459 sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge 460 461 // Watchdog timer (WDT) for MISS timeout exception (black-hole detection) 462 sc_signal<uint32_t> r_dcache_miss_wdt_max; // wdt triggering value 463 sc_signal<uint32_t> r_dcache_miss_wdt; // wdt counter 459 464 460 465 // handling coherence requests 461 466 sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval 462 467 sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval 463 sc_signal<size_t> r_dcache_cc_word; 468 sc_signal<size_t> r_dcache_cc_word; // word counter for cc update 464 469 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 465 470 466 471 // coherence clack handling 467 472 sc_signal<bool> r_dcache_clack_req; // clack request 468 sc_signal<size_t> r_dcache_clack_way; 469 sc_signal<size_t> r_dcache_clack_set; 473 sc_signal<size_t> r_dcache_clack_way; // clack way 474 sc_signal<size_t> r_dcache_clack_set; // clack set 470 475 471 476 // dcache flush handling 472 sc_signal<size_t> r_dcache_flush_count; 477 sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush 473 478 474 479 // ll response handling 475 sc_signal<size_t> r_dcache_ll_rsp_count; 480 sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp 476 481 477 482 // used by the TLB miss sub-fsm 478 sc_signal<uint32_t> r_dcache_tlb_vaddr; 479 sc_signal<bool> r_dcache_tlb_ins; 480 sc_signal<paddr_t> r_dcache_tlb_paddr; 481 sc_signal<uint32_t> r_dcache_tlb_pte_flags; 482 sc_signal<uint32_t> r_dcache_tlb_pte_ppn; 483 sc_signal<size_t> r_dcache_tlb_cache_way; 484 sc_signal<size_t> r_dcache_tlb_cache_set; 483 sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss 484 sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) 485 sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte 486 sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 487 sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 488 sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache 489 sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache 485 490 sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache 486 sc_signal<size_t> r_dcache_tlb_way; 487 sc_signal<size_t> r_dcache_tlb_set; 491 sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb 492 sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb 488 493 489 494 // ITLB and DTLB invalidation … … 519 524 sc_signal<size_t> r_vci_cmd_min; // used for write bursts 520 525 sc_signal<size_t> r_vci_cmd_max; // used for write bursts 521 sc_signal<size_t> r_vci_cmd_cpt; 522 sc_signal<bool> r_vci_cmd_imiss_prio; 526 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts 527 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss 523 528 524 529 /////////////////////////////////// … … 529 534 sc_signal<bool> r_vci_rsp_ins_error; 530 535 sc_signal<bool> r_vci_rsp_data_error; 531 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; 532 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; 536 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 537 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 533 538 534 539 /////////////////////////////////// … … 551 556 552 557 // communication between CC_RECEIVE FSM and ICACHE FSM 553 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request554 sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request555 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way556 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set557 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; 558 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request 559 sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request 560 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way 561 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set 562 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index 558 563 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address 559 564 560 565 // communication between CC_RECEIVE FSM and DCACHE FSM 561 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request562 sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request563 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way564 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set565 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; 566 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request 567 sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request 568 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way 569 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set 570 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index 566 571 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 567 572
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