Index: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 840)
+++ branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 845)
@@ -266,4 +266,5 @@
         MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
         MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read & Bus Error in cache access
+        MMU_READ_DATA_TIMEOUT         = 0x1200, // Read & Watchdog timeout
     };
 
@@ -433,6 +434,6 @@
 
     // communication between DCACHE FSM and VCI_CMD FSM
-    sc_signal<paddr_t>      r_dcache_vci_paddr;            // physical address for VCI command
-    sc_signal<uint32_t>     r_dcache_vci_wdata;            // write unc data for VCI command
+    sc_signal<paddr_t>      r_dcache_vci_paddr;         // physical address for VCI command
+    sc_signal<uint32_t>     r_dcache_vci_wdata;         // write unc data for VCI command
     sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
     sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
@@ -447,43 +448,47 @@
 
     // register used for XTN inval
-    sc_signal<size_t>       r_dcache_xtn_way;            // selected way (from dcache)
-    sc_signal<size_t>       r_dcache_xtn_set;            // selected set (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_way;           // selected way (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_set;           // selected set (from dcache)
 
     // handling dcache miss
-    sc_signal<int>            r_dcache_miss_type;            // depending on the requester
-    sc_signal<size_t>       r_dcache_miss_word;            // word index for cache update
-    sc_signal<size_t>       r_dcache_miss_way;            // selected way for cache update
-    sc_signal<size_t>       r_dcache_miss_set;            // selected set for cache update
+    sc_signal<int>          r_dcache_miss_type;         // depending on the requester
+    sc_signal<size_t>       r_dcache_miss_word;         // word index for cache update
+    sc_signal<size_t>       r_dcache_miss_way;          // selected way for cache update
+    sc_signal<size_t>       r_dcache_miss_set;          // selected set for cache update
     sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
     sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
+
+    // Watchdog timer (WDT) for MISS timeout exception (black-hole detection)
+    sc_signal<uint32_t>     r_dcache_miss_wdt_max;      // wdt triggering value
+    sc_signal<uint32_t>     r_dcache_miss_wdt;          // wdt counter
 
     // handling coherence requests
     sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
     sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
-    sc_signal<size_t>       r_dcache_cc_word;            // word counter for cc update
+    sc_signal<size_t>       r_dcache_cc_word;           // word counter for cc update
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
 
     // coherence clack handling
     sc_signal<bool>         r_dcache_clack_req;         // clack request
-    sc_signal<size_t>       r_dcache_clack_way;            // clack way
-    sc_signal<size_t>       r_dcache_clack_set;            // clack set
+    sc_signal<size_t>       r_dcache_clack_way;         // clack way
+    sc_signal<size_t>       r_dcache_clack_set;         // clack set
 
     // dcache flush handling
-    sc_signal<size_t>       r_dcache_flush_count;        // slot counter used for cache flush
+    sc_signal<size_t>       r_dcache_flush_count;       // slot counter used for cache flush
 
     // ll response handling
-    sc_signal<size_t>       r_dcache_ll_rsp_count;        // flit counter used for ll rsp
+    sc_signal<size_t>       r_dcache_ll_rsp_count;      // flit counter used for ll rsp
 
     // used by the TLB miss sub-fsm
-    sc_signal<uint32_t>     r_dcache_tlb_vaddr;            // virtual address for a tlb miss
-    sc_signal<bool>         r_dcache_tlb_ins;            // target tlb (itlb if true)
-    sc_signal<paddr_t>      r_dcache_tlb_paddr;            // physical address of pte
-    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;        // pte1 or first word of pte2
-    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;        // second word of pte2
-    sc_signal<size_t>       r_dcache_tlb_cache_way;        // selected way in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_set;        // selected set in dcache
+    sc_signal<uint32_t>     r_dcache_tlb_vaddr;         // virtual address for a tlb miss
+    sc_signal<bool>         r_dcache_tlb_ins;           // target tlb (itlb if true)
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of pte
+    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;     // pte1 or first word of pte2
+    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;       // second word of pte2
+    sc_signal<size_t>       r_dcache_tlb_cache_way;     // selected way in dcache
+    sc_signal<size_t>       r_dcache_tlb_cache_set;     // selected set in dcache
     sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
-    sc_signal<size_t>       r_dcache_tlb_way;            // selected way in tlb
-    sc_signal<size_t>       r_dcache_tlb_set;            // selected set in tlb
+    sc_signal<size_t>       r_dcache_tlb_way;           // selected way in tlb
+    sc_signal<size_t>       r_dcache_tlb_set;           // selected set in tlb
 
     // ITLB and DTLB invalidation
@@ -519,6 +524,6 @@
     sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
     sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_cpt;                    // used for write bursts
-    sc_signal<bool>         r_vci_cmd_imiss_prio;            // round-robin between imiss & dmiss
+    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
+    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
 
     ///////////////////////////////////
@@ -529,6 +534,6 @@
     sc_signal<bool>         r_vci_rsp_ins_error;
     sc_signal<bool>         r_vci_rsp_data_error;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;            // response FIFO to ICACHE FSM
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;            // response FIFO to DCACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
 
     ///////////////////////////////////
@@ -551,17 +556,17 @@
 
     // communication between CC_RECEIVE FSM and ICACHE FSM
-    sc_signal<bool>         r_cc_receive_icache_req;        // cc_receive to icache request
-    sc_signal<int>          r_cc_receive_icache_type;       // cc_receive type of request
-    sc_signal<size_t>       r_cc_receive_icache_way;        // cc_receive to icache way
-    sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
-    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
+    sc_signal<bool>         r_cc_receive_icache_req;          // cc_receive to icache request
+    sc_signal<int>          r_cc_receive_icache_type;         // cc_receive type of request
+    sc_signal<size_t>       r_cc_receive_icache_way;          // cc_receive to icache way
+    sc_signal<size_t>       r_cc_receive_icache_set;          // cc_receive to icache set
+    sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx; // cc_receive update table index
     sc_signal<paddr_t>      r_cc_receive_icache_nline;        // cache line physical address
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
-    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
-    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
-    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
-    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
-    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
+    sc_signal<bool>         r_cc_receive_dcache_req;          // cc_receive to dcache request
+    sc_signal<int>          r_cc_receive_dcache_type;         // cc_receive type of request
+    sc_signal<size_t>       r_cc_receive_dcache_way;          // cc_receive to dcache way
+    sc_signal<size_t>       r_cc_receive_dcache_set;          // cc_receive to dcache set
+    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index
     sc_signal<paddr_t>      r_cc_receive_dcache_nline;        // cache line physical address
 
