- Timestamp:
- Oct 16, 2014, 10:57:42 AM (10 years ago)
- File:
-
- 1 edited
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branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r840 r845 331 331 r_dcache_miss_set("r_dcache_miss_set"), 332 332 r_dcache_miss_inval("r_dcache_miss_inval"), 333 r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"), 334 r_dcache_miss_wdt("r_dcache_miss_wdt"), 333 335 334 336 r_dcache_cc_way("r_dcache_cc_way"), … … 811 813 812 814 r_dcache_clack_req = false; 815 816 // Reset watchdog timer threshold to max value 817 r_dcache_miss_wdt_max = UINT32_MAX; 813 818 814 819 // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs … … 4142 4147 r_dcache_miss_set = set; 4143 4148 4149 // reset to 0 the miss watchdog timer 4150 r_dcache_miss_wdt = 0; 4151 4144 4152 if (cleanup) 4145 4153 { … … 4265 4273 r_dcache_fsm = DCACHE_CC_CHECK; 4266 4274 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4275 break; 4276 } 4277 4278 // increment MISS watchdog timer for black-hole detection 4279 r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1; 4280 if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) { 4281 r_mmu_detr = MMU_READ_DATA_TIMEOUT; 4282 r_mmu_dbvar = r_dcache_save_vaddr.read(); 4283 m_drsp.valid = true; 4284 m_drsp.error = true; 4285 r_dcache_fsm = DCACHE_IDLE; 4267 4286 break; 4268 4287 }
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