Changeset 853

Timestamp:

Oct 21, 2014, 5:16:36 PM (10 years ago)

Author:

cfuguet

Message:

reconf: introducing assert to detect early watchdog timeout.

• Introducing an assert in the vci_cc_vcache_wrapper component. An early watchdog timeout arises when the timeout threshold is less than the max latency of a read miss transaction.

Location:

branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source

Files:

• include/vci_cc_vcache_wrapper.h (modified) (3 diffs)
• src/vci_cc_vcache_wrapper.cpp (modified) (9 diffs)

branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -65 +65 @@
 
     typedef typename vci_param::fast_addr_t  paddr_t;
+    typedef typename vci_param::fast_trdid_t trdid_t;
 
     enum icache_fsm_state_e
@@ -441 +442 @@
     sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
     sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
+    sc_signal<trdid_t>      r_dcache_vci_miss_trdid;    // miss dcache trdid (for debug)
 
     // register used for XTN inval
@@ -457 +459 @@
     sc_signal<uint32_t>     r_dcache_miss_wdt_max;      // wdt triggering value
     sc_signal<uint32_t>     r_dcache_miss_wdt;          // wdt counter
+    sc_signal<trdid_t>      r_dcache_wdt_timeout;       // timeout counter (for debug)
 
     // handling coherence requests

branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -322 +322 @@
       r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
       r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
+      r_dcache_vci_miss_trdid("r_dcache_vci_miss_trdid"),
 
       r_dcache_xtn_way("r_dcache_xtn_way"),
@@ -333 +334 @@
       r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"),
       r_dcache_miss_wdt("r_dcache_miss_wdt"),
+      r_dcache_wdt_timeout("r_dcache_wdt_timeout"),
 
       r_dcache_cc_way("r_dcache_cc_way"),
@@ -816 +818 @@
         // Reset watchdog timer threshold to max value
         r_dcache_miss_wdt_max      = UINT32_MAX;
+        r_dcache_wdt_timeout       = 0;
 
         // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
@@ -2799 +2802 @@
 #endif
                                 // request a VCI DMISS transaction
+                                r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
+
                                 r_dcache_vci_paddr    = paddr;
                                 r_dcache_vci_miss_req = true;
@@ -3194 +3199 @@
         else // we must load the missing cache line in dcache
         {
+            r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
+
             r_dcache_vci_miss_req = true;
             r_dcache_vci_paddr    = r_dcache_tlb_paddr.read();
@@ -3469 +3476 @@
         else            // we must load the missing cache line in dcache
         {
+            r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
+
             r_dcache_fsm          = DCACHE_MISS_SELECT;
             r_dcache_vci_miss_req = true;
@@ -4296 +4305 @@
             m_drsp.error = true;
             r_dcache_fsm = DCACHE_IDLE;
+
+            // debug: this counter is used to detect an early WDT timeout.
+            // It is sent as the data miss transactions TRDID. When a data miss
+            // response is treated by the RSP FSM, the RTRDID is compared to
+            // this counter to determine if a timeout was triggered during the
+            // transaction.
+            r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
+
+#if DEBUG_DCACHE
+            if (m_debug_dcache_fsm)
+            {
+                std::cout << "  <PROC " << name() << " DCACHE_MISS_WAIT>"
+                             "  watchdog timer exception" << std::endl;
+            }
+#endif
             break;
         }
@@ -5371 +5395 @@
             r_vci_rsp_cpt = 0;
 
-            if ((p_vci.rpktid.read() & 0x7) ==  TYPE_DATA_UNC)
+            if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
             {
                 r_vci_rsp_fsm = RSP_DATA_UNC;
             }
-            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_READ_DATA_MISS)
-            {
+            else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
+            {
+                // debug: verify that the available response concerns the current transaction.
+                assert(r_dcache_wdt_timeout.read() == p_vci.rtrdid.read());
+
                 r_vci_rsp_fsm = RSP_DATA_MISS;
             }
-            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_READ_INS_UNC)
+            else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
             {
                 r_vci_rsp_fsm = RSP_INS_UNC;
             }
-            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_READ_INS_MISS)
+            else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
             {
                 r_vci_rsp_fsm = RSP_INS_MISS;
             }
-            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_WRITE)
+            else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
             {
                 r_vci_rsp_fsm = RSP_DATA_WRITE;
             }
-            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_CAS)
+            else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
             {
                 r_vci_rsp_fsm = RSP_DATA_UNC;
             }
-            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_LL)
+            else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
             {
                 r_vci_rsp_fsm = RSP_DATA_LL;
@@ -6074 +6101 @@
         p_vci.wdata   = 0;
         p_vci.be      = 0xF;
-        p_vci.trdid   = 0;
+        p_vci.trdid   = r_dcache_vci_miss_trdid.read();
         p_vci.pktid   = TYPE_READ_DATA_MISS;
         p_vci.plen    = m_dcache_words << 2;