Changeset 855 for branches/reconfiguration/platforms/tsar_generic_iob
- Timestamp:
- Oct 21, 2014, 5:52:59 PM (10 years ago)
- Location:
- branches/reconfiguration/platforms/tsar_generic_iob
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/reconfiguration/platforms/tsar_generic_iob/scripts/onerun.py
r847 r855 39 39 '--batch-mode', '-b', dest='batchmode', action='store_true', 40 40 help='run simulation in batch mode: no interactive TTY or FrameBuffer') 41 42 parser.add_argument( 43 '--faulty-router', '-f', dest='faultyrouter', default=-1, 44 help='ID (X,Y) of faulty router') 45 46 parser.add_argument( 47 '--debug', '-g', dest='debug', nargs=4, 48 help='needs four arguments: from, to, procid, memcid') 41 49 42 50 args = parser.parse_args() … … 117 125 command.extend(["-DISK", "/dev/null"]) 118 126 command.extend(["-THREADS", str(ompthreads)]) 119 command.extend(["-NCYCLES", "1000000"]) 127 128 if args.faultyrouter != -1: 129 command.extend(["-FAULTY_ROUTER", str(args.faultyrouter)]) 130 131 if args.debug != None: 132 command.extend(["-DEBUG", str(args.debug[0])]); 133 command.extend(["-NCYCLES", str(args.debug[1])]); 134 command.extend(["-PROCID", str(args.debug[2])]); 135 command.extend(["-MEMCID", str(args.debug[3])]); 136 else: 137 command.extend(["-NCYCLES", "1000000"]) 138 120 139 subprocess.call(command, stdout=logfile, stderr=logfile) 121 140 -
branches/reconfiguration/platforms/tsar_generic_iob/top.cpp
r806 r855 55 55 // - IRQ_IN[4] : DMA channel 3 56 56 // 57 // All clusters are identical, but cluster(0, 0) and cluster(X_SIZE-1,Y_SIZE-1)57 // All clusters are identical, but cluster(0, 0) and cluster(X_SIZE-1, Y_SIZE-1) 58 58 // contain an extra IO bridge component. These IOB0 & IOB1 components are 59 59 // connected to the three networks (INT, RAM, IOX). … … 213 213 #define WEST 3 214 214 215 #define cluster(x, y) ((y) + ((x) << 4))215 #define cluster(x, y) ((y) + ((x) << Y_WIDTH)) 216 216 217 217 //////////////////////////////////////////////////////////// … … 234 234 // in the hard_config.h file. For replicated segments, the 235 235 // base address is incremented by a cluster offset: 236 // offset = cluster(x, y) << (address_width-X_WIDTH-Y_WIDTH);236 // offset = cluster(x, y) << (address_width-X_WIDTH-Y_WIDTH); 237 237 238 238 //////////////////////////////////////////////////////////////////////// … … 318 318 319 319 320 char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code 321 size_t ncycles = UINT_MAX; // simulated cycles 322 char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image 323 char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file 324 char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file 325 ssize_t threads_nr = 1; // simulator's threads number 326 bool debug_ok = false; // trace activated 327 size_t debug_period = 1; // trace period 328 size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc 329 size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc 330 size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram 331 bool debug_iob = false; // trace iob0 & iob1 when true 332 uint32_t debug_from = 0; // trace start cycle 333 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 334 size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 335 size_t cluster_iob1 = cluster(X_SIZE-1,Y_SIZE-1); // cluster containing IOB1 320 char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code 321 size_t ncycles = UINT_MAX; // simulated cycles 322 char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image 323 char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file 324 char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file 325 ssize_t threads_nr = 1; // simulator's threads number 326 size_t faulty_router_id = 0xFFFFFFFF; // faulty router coordinates 327 bool debug_ok = false; // trace activated 328 size_t debug_period = 1; // trace period 329 size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc 330 size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc 331 size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram 332 bool debug_iob = false; // trace iob0 & iob1 when true 333 uint32_t debug_from = 0; // trace start cycle 334 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 335 size_t cluster_iob0 = cluster(0, 0); // cluster containing IOB0 336 size_t cluster_iob1 = cluster(X_SIZE-1, Y_SIZE-1); // cluster containing IOB1 336 337 337 338 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and … … 343 344 for (int n = 1; n < argc; n = n + 2) 344 345 { 345 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n+1<argc))346 if ((strcmp(argv[n], "-NCYCLES") == 0) && (n+1<argc)) 346 347 { 347 348 ncycles = strtol(argv[n+1], NULL, 0); 348 349 } 349 else if ((strcmp(argv[n], "-SOFT") == 0) && (n+1<argc) )350 else if ((strcmp(argv[n], "-SOFT") == 0) && (n+1<argc) ) 350 351 { 351 352 strcpy(soft_name, argv[n+1]); 352 353 } 353 else if ((strcmp(argv[n], "-DEBUG") == 0) && (n+1<argc) )354 else if ((strcmp(argv[n], "-DEBUG") == 0) && (n+1<argc) ) 354 355 { 355 356 debug_ok = true; 356 357 debug_from = strtol(argv[n+1], NULL, 0); 357 358 } 358 else if ((strcmp(argv[n], "-DISK") == 0) && (n+1<argc) )359 else if ((strcmp(argv[n], "-DISK") == 0) && (n+1<argc) ) 359 360 { 360 361 strcpy(disk_name, argv[n+1]); 361 362 } 362 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n+1<argc) )363 else if ((strcmp(argv[n], "-MEMCID") == 0) && (n+1<argc) ) 363 364 { 364 365 debug_memc_id = strtol(argv[n+1], NULL, 0); 365 size_t x = debug_memc_id >> 4;366 size_t y = debug_memc_id & 0xF;366 size_t x = debug_memc_id >> Y_WIDTH; 367 size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); 367 368 if( (x>=X_SIZE) || (y>=Y_SIZE) ) 368 369 { … … 371 372 } 372 373 } 373 else if ((strcmp(argv[n], "-XRAMID") == 0) && (n+1<argc) )374 else if ((strcmp(argv[n], "-XRAMID") == 0) && (n+1<argc) ) 374 375 { 375 376 debug_xram_id = strtol(argv[n+1], NULL, 0); 376 size_t x = debug_xram_id >> 4;377 size_t y = debug_xram_id & 0xF;377 size_t x = debug_xram_id >> Y_WIDTH; 378 size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); 378 379 if( (x>=X_SIZE) || (y>=Y_SIZE) ) 379 380 { … … 382 383 } 383 384 } 384 else if ((strcmp(argv[n], "-IOB") == 0) && (n+1<argc) )385 else if ((strcmp(argv[n], "-IOB") == 0) && (n+1<argc) ) 385 386 { 386 387 debug_iob = strtol(argv[n+1], NULL, 0); 387 388 } 388 else if ((strcmp(argv[n], "-PROCID") == 0) && (n+1<argc) )389 else if ((strcmp(argv[n], "-PROCID") == 0) && (n+1<argc) ) 389 390 { 390 391 debug_proc_id = strtol(argv[n+1], NULL, 0); 391 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX;392 size_t x = cluster_xy >> 4;393 size_t y = cluster_xy & 0xF;392 size_t cluster_xy = debug_proc_id >> P_WIDTH; 393 size_t x = cluster_xy >> Y_WIDTH; 394 size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); 394 395 if( (x>=X_SIZE) || (y>=Y_SIZE) ) 395 396 { … … 411 412 debug_period = strtol(argv[n+1], NULL, 0); 412 413 } 414 else if ((strcmp(argv[n], "-FAULTY_ROUTER") == 0) && (n+1 < argc) ) 415 { 416 faulty_router_id = strtol(argv[n+1], NULL, 0); 417 size_t x = faulty_router_id >> Y_WIDTH; 418 size_t y = faulty_router_id & ((1 << Y_WIDTH) - 1); 419 if( (x>=X_SIZE) || (y>=Y_SIZE) ) 420 { 421 std::cout << "FAULTY_ROUTER parameter doesn't fit X_SIZE/Y_SIZE" << std::endl; 422 exit(0); 423 } 424 } 413 425 else 414 426 { 415 std::cout << " Arguments are (key, value) couples." << std::endl;427 std::cout << " Arguments are (key, value) couples." << std::endl; 416 428 std::cout << " The order is not important." << std::endl; 417 429 std::cout << " Accepted arguments are :" << std::endl << std::endl; … … 522 534 for (size_t y = 0; y < Y_SIZE; y++) 523 535 { 524 uint64_t offset = ((uint64_t)cluster(x, y))536 uint64_t offset = ((uint64_t)cluster(x, y)) 525 537 << (vci_address_width-X_WIDTH-Y_WIDTH); 526 538 bool config = true; … … 532 544 smemc_conf << "int_seg_memc_conf_" << x << "_" << y; 533 545 maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, 534 IntTab(cluster(x, y), INT_MEMC_TGT_ID), not cacheable, config ));546 IntTab(cluster(x, y), INT_MEMC_TGT_ID), not cacheable, config )); 535 547 536 548 std::ostringstream smemc_xram; 537 549 smemc_xram << "int_seg_memc_xram_" << x << "_" << y; 538 550 maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, 539 IntTab(cluster(x, y), INT_MEMC_TGT_ID), cacheable));551 IntTab(cluster(x, y), INT_MEMC_TGT_ID), cacheable)); 540 552 541 553 std::ostringstream sxicu; 542 554 sxicu << "int_seg_xicu_" << x << "_" << y; 543 555 maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, 544 IntTab(cluster(x, y), INT_XICU_TGT_ID), not cacheable));556 IntTab(cluster(x, y), INT_XICU_TGT_ID), not cacheable)); 545 557 546 558 std::ostringstream smdma; 547 559 smdma << "int_seg_mdma_" << x << "_" << y; 548 560 maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, 549 IntTab(cluster(x, y), INT_MDMA_TGT_ID), not cacheable));561 IntTab(cluster(x, y), INT_MDMA_TGT_ID), not cacheable)); 550 562 551 563 std::ostringstream sbrom; 552 564 sbrom << "int_seg_brom_" << x << "_" << y; 553 565 maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, 554 IntTab(cluster(x, y), INT_BROM_TGT_ID), cacheable));566 IntTab(cluster(x, y), INT_BROM_TGT_ID), cacheable)); 555 567 556 568 // the following segments are only defined in cluster_iob0 or in cluster_iob1 557 569 558 if ( (cluster(x, y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) )570 if ( (cluster(x, y) == cluster_iob0) or (cluster(x, y) == cluster_iob1) ) 559 571 { 560 572 std::ostringstream siobx; 561 573 siobx << "int_seg_iobx_" << x << "_" << y; 562 574 maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, 563 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable, config ));575 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable, config )); 564 576 565 577 std::ostringstream stty; 566 578 stty << "int_seg_mtty_" << x << "_" << y; 567 579 maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, 568 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable));580 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); 569 581 570 582 std::ostringstream sfbf; 571 583 sfbf << "int_seg_fbuf_" << x << "_" << y; 572 584 maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, 573 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable));585 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); 574 586 575 587 std::ostringstream sbdv; 576 588 sbdv << "int_seg_bdev_" << x << "_" << y; 577 589 maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, 578 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable));590 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); 579 591 580 592 std::ostringstream snic; 581 593 snic << "int_seg_mnic_" << x << "_" << y; 582 594 maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, 583 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable));595 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); 584 596 585 597 std::ostringstream sdma; 586 598 sdma << "int_seg_cdma_" << x << "_" << y; 587 599 maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, 588 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable));600 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); 589 601 590 602 std::ostringstream spic; 591 603 spic << "int_seg_iopi_" << x << "_" << y; 592 604 maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, 593 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable));605 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); 594 606 595 607 std::ostringstream ssim; 596 608 ssim << "int_seg_simh_" << x << "_" << y; 597 609 maptab_int.add(Segment(ssim.str(), SEG_SIM_BASE+offset, SEG_SIM_SIZE, 598 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable));610 IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); 599 611 } 600 612 … … 602 614 // and the port index on the local interconnect. 603 615 604 maptab_int.srcid_map( IntTab( cluster(x, y), MDMA_LOCAL_SRCID ),605 IntTab( cluster(x, y), INT_MDMA_INI_ID ) );606 607 maptab_int.srcid_map( IntTab( cluster(x, y), IOBX_LOCAL_SRCID ),608 IntTab( cluster(x, y), INT_IOBX_INI_ID ) );609 610 maptab_int.srcid_map( IntTab( cluster(x, y), IOPI_LOCAL_SRCID ),611 IntTab( cluster(x, y), INT_IOBX_INI_ID ) );616 maptab_int.srcid_map( IntTab( cluster(x, y), MDMA_LOCAL_SRCID ), 617 IntTab( cluster(x, y), INT_MDMA_INI_ID ) ); 618 619 maptab_int.srcid_map( IntTab( cluster(x, y), IOBX_LOCAL_SRCID ), 620 IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); 621 622 maptab_int.srcid_map( IntTab( cluster(x, y), IOPI_LOCAL_SRCID ), 623 IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); 612 624 613 625 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) 614 maptab_int.srcid_map( IntTab( cluster(x, y), PROC_LOCAL_SRCID+p ),615 IntTab( cluster(x, y), INT_PROC_INI_ID+p ) );626 maptab_int.srcid_map( IntTab( cluster(x, y), PROC_LOCAL_SRCID+p ), 627 IntTab( cluster(x, y), INT_PROC_INI_ID+p ) ); 616 628 } 617 629 } … … 635 647 for (size_t y = 0; y < Y_SIZE ; y++) 636 648 { 637 uint64_t offset = ((uint64_t)cluster(x, y))649 uint64_t offset = ((uint64_t)cluster(x, y)) 638 650 << (vci_address_width-X_WIDTH-Y_WIDTH); 639 651 … … 641 653 sxram << "ext_seg_xram_" << x << "_" << y; 642 654 maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, 643 SEG_RAM_SIZE, IntTab(cluster(x, y), RAM_XRAM_TGT_ID), false));655 SEG_RAM_SIZE, IntTab(cluster(x, y), RAM_XRAM_TGT_ID), false)); 644 656 } 645 657 } … … 745 757 const bool cacheable = true; 746 758 747 const uint64_t offset = ((uint64_t)cluster(x, y))759 const uint64_t offset = ((uint64_t)cluster(x, y)) 748 760 << (vci_address_width-X_WIDTH-Y_WIDTH); 749 761 … … 1018 1030 std::cout << std::endl; 1019 1031 1020 const bool is_iob0 = (cluster(x, y) == cluster_iob0);1021 const bool is_iob1 = (cluster(x, y) == cluster_iob1);1032 const bool is_iob0 = (cluster(x, y) == cluster_iob0); 1033 const bool is_iob1 = (cluster(x, y) == cluster_iob1); 1022 1034 const bool is_io_cluster = is_iob0 || is_iob1; 1023 1035 … … 1090 1102 frozen_cycles, 1091 1103 debug_from, 1092 debug_ok and (cluster(x, y) == debug_memc_id),1093 debug_ok and (cluster(x, y) == debug_proc_id),1104 debug_ok and (cluster(x, y) == debug_memc_id), 1105 debug_ok and (cluster(x, y) == (debug_proc_id >> P_WIDTH)), 1094 1106 debug_ok and debug_iob 1095 1107 ); … … 1102 1114 } 1103 1115 #endif 1116 1117 // disable all interfaces of the faulty router 1118 if (faulty_router_id != 0xFFFFFFFF) 1119 { 1120 int faulty_x = faulty_router_id >> Y_WIDTH; 1121 int faulty_y = faulty_router_id & ((1 << Y_WIDTH) - 1); 1122 clusters[faulty_x][faulty_y]->int_router_cmd[0]->set_disable_mask(0x1F); 1123 } 1104 1124 1105 1125 std::cout << std::endl; … … 1414 1434 1415 1435 // simulation loop 1416 struct timeval t1, t2;1436 struct timeval t1, t2; 1417 1437 1418 1438 // cycles between stats … … 1457 1477 if ( debug_proc_id != 0xFFFFFFFF ) 1458 1478 { 1459 size_t l = debug_proc_id % NB_PROCS_MAX;1460 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX;1461 size_t x = cluster_xy >> 4;1462 size_t y = cluster_xy & 0xF;1479 size_t l = debug_proc_id & ((1 << P_WIDTH) - 1); 1480 size_t cluster_xy = debug_proc_id >> P_WIDTH ; 1481 size_t x = cluster_xy >> Y_WIDTH; 1482 size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); 1463 1483 1464 1484 clusters[x][y]->proc[l]->print_trace(1); … … 1485 1505 if ( debug_memc_id != 0xFFFFFFFF ) 1486 1506 { 1487 size_t x = debug_memc_id >> 4;1488 size_t y = debug_memc_id & 0xF;1507 size_t x = debug_memc_id >> Y_WIDTH; 1508 size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); 1489 1509 1490 1510 clusters[x][y]->memc->print_trace(0); … … 1506 1526 if ( debug_xram_id != 0xFFFFFFFF ) 1507 1527 { 1508 size_t x = debug_xram_id >> 4;1509 size_t y = debug_xram_id & 0xF;1528 size_t x = debug_xram_id >> Y_WIDTH; 1529 size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); 1510 1530 1511 1531 clusters[x][y]->xram->print_trace(); -
branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
r851 r855 78 78 dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), 79 79 80 Uses('caba: dspin_router',80 Uses('caba:reconf:dspin_router', 81 81 flit_width = parameter.Reference('dspin_int_cmd_width')), 82 82 83 Uses('caba: dspin_router',83 Uses('caba:reconf:dspin_router', 84 84 flit_width = parameter.Reference('dspin_int_rsp_width')), 85 85 … … 95 95 dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), 96 96 97 Uses('caba: dspin_router',97 Uses('caba:reconf:dspin_router', 98 98 flit_width = parameter.Reference('dspin_ram_cmd_width')), 99 99 100 Uses('caba: dspin_router',100 Uses('caba:reconf:dspin_router', 101 101 flit_width = parameter.Reference('dspin_ram_rsp_width')), 102 102
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