Index: /branches/reconfiguration/platforms/tsar_generic_iob/scripts/onerun.py =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/scripts/onerun.py (revision 854) +++ /branches/reconfiguration/platforms/tsar_generic_iob/scripts/onerun.py (revision 855) @@ -39,4 +39,12 @@ '--batch-mode', '-b', dest='batchmode', action='store_true', help='run simulation in batch mode: no interactive TTY or FrameBuffer') + +parser.add_argument( + '--faulty-router', '-f', dest='faultyrouter', default=-1, + help='ID (X,Y) of faulty router') + +parser.add_argument( + '--debug', '-g', dest='debug', nargs=4, + help='needs four arguments: from, to, procid, memcid') args = parser.parse_args() @@ -117,5 +125,16 @@ command.extend(["-DISK", "/dev/null"]) command.extend(["-THREADS", str(ompthreads)]) -command.extend(["-NCYCLES", "1000000"]) + +if args.faultyrouter != -1: + command.extend(["-FAULTY_ROUTER", str(args.faultyrouter)]) + +if args.debug != None: + command.extend(["-DEBUG", str(args.debug[0])]); + command.extend(["-NCYCLES", str(args.debug[1])]); + command.extend(["-PROCID", str(args.debug[2])]); + command.extend(["-MEMCID", str(args.debug[3])]); +else: + command.extend(["-NCYCLES", "1000000"]) + subprocess.call(command, stdout=logfile, stderr=logfile) Index: /branches/reconfiguration/platforms/tsar_generic_iob/top.cpp =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/top.cpp (revision 854) +++ /branches/reconfiguration/platforms/tsar_generic_iob/top.cpp (revision 855) @@ -55,5 +55,5 @@ // - IRQ_IN[4] : DMA channel 3 // -// All clusters are identical, but cluster(0,0) and cluster(X_SIZE-1,Y_SIZE-1) +// All clusters are identical, but cluster(0, 0) and cluster(X_SIZE-1, Y_SIZE-1) // contain an extra IO bridge component. These IOB0 & IOB1 components are // connected to the three networks (INT, RAM, IOX). @@ -213,5 +213,5 @@ #define WEST 3 -#define cluster(x,y) ((y) + ((x) << 4)) +#define cluster(x, y) ((y) + ((x) << Y_WIDTH)) //////////////////////////////////////////////////////////// @@ -234,5 +234,5 @@ // in the hard_config.h file. For replicated segments, the // base address is incremented by a cluster offset: -// offset = cluster(x,y) << (address_width-X_WIDTH-Y_WIDTH); +// offset = cluster(x, y) << (address_width-X_WIDTH-Y_WIDTH); //////////////////////////////////////////////////////////////////////// @@ -318,20 +318,21 @@ - char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code - size_t ncycles = UINT_MAX; // simulated cycles - char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image - char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file - char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file - ssize_t threads_nr = 1; // simulator's threads number - bool debug_ok = false; // trace activated - size_t debug_period = 1; // trace period - size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc - size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc - size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram - bool debug_iob = false; // trace iob0 & iob1 when true - uint32_t debug_from = 0; // trace start cycle - uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor - size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 - size_t cluster_iob1 = cluster(X_SIZE-1,Y_SIZE-1); // cluster containing IOB1 + char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code + size_t ncycles = UINT_MAX; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file + ssize_t threads_nr = 1; // simulator's threads number + size_t faulty_router_id = 0xFFFFFFFF; // faulty router coordinates + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc + size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc + size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram + bool debug_iob = false; // trace iob0 & iob1 when true + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_iob0 = cluster(0, 0); // cluster containing IOB0 + size_t cluster_iob1 = cluster(X_SIZE-1, Y_SIZE-1); // cluster containing IOB1 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and @@ -343,26 +344,26 @@ for (int n = 1; n < argc; n = n + 2) { - if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1> 4; - size_t y = debug_memc_id & 0xF; + size_t x = debug_memc_id >> Y_WIDTH; + size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); if( (x>=X_SIZE) || (y>=Y_SIZE) ) { @@ -371,9 +372,9 @@ } } - else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1> 4; - size_t y = debug_xram_id & 0xF; + size_t x = debug_xram_id >> Y_WIDTH; + size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); if( (x>=X_SIZE) || (y>=Y_SIZE) ) { @@ -382,14 +383,14 @@ } } - else if ((strcmp(argv[n],"-IOB") == 0) && (n+1> 4; - size_t y = cluster_xy & 0xF; + size_t cluster_xy = debug_proc_id >> P_WIDTH; + size_t x = cluster_xy >> Y_WIDTH; + size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); if( (x>=X_SIZE) || (y>=Y_SIZE) ) { @@ -411,7 +412,18 @@ debug_period = strtol(argv[n+1], NULL, 0); } + else if ((strcmp(argv[n], "-FAULTY_ROUTER") == 0) && (n+1 < argc) ) + { + faulty_router_id = strtol(argv[n+1], NULL, 0); + size_t x = faulty_router_id >> Y_WIDTH; + size_t y = faulty_router_id & ((1 << Y_WIDTH) - 1); + if( (x>=X_SIZE) || (y>=Y_SIZE) ) + { + std::cout << "FAULTY_ROUTER parameter doesn't fit X_SIZE/Y_SIZE" << std::endl; + exit(0); + } + } else { - std::cout << " Arguments are (key,value) couples." << std::endl; + std::cout << " Arguments are (key, value) couples." << std::endl; std::cout << " The order is not important." << std::endl; std::cout << " Accepted arguments are :" << std::endl << std::endl; @@ -522,5 +534,5 @@ for (size_t y = 0; y < Y_SIZE; y++) { - uint64_t offset = ((uint64_t)cluster(x,y)) + uint64_t offset = ((uint64_t)cluster(x, y)) << (vci_address_width-X_WIDTH-Y_WIDTH); bool config = true; @@ -532,69 +544,69 @@ smemc_conf << "int_seg_memc_conf_" << x << "_" << y; maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, - IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); + IntTab(cluster(x, y), INT_MEMC_TGT_ID), not cacheable, config )); std::ostringstream smemc_xram; smemc_xram << "int_seg_memc_xram_" << x << "_" << y; maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, - IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); + IntTab(cluster(x, y), INT_MEMC_TGT_ID), cacheable)); std::ostringstream sxicu; sxicu << "int_seg_xicu_" << x << "_" << y; maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, - IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_XICU_TGT_ID), not cacheable)); std::ostringstream smdma; smdma << "int_seg_mdma_" << x << "_" << y; maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, - IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_MDMA_TGT_ID), not cacheable)); std::ostringstream sbrom; sbrom << "int_seg_brom_" << x << "_" << y; maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, - IntTab(cluster(x,y), INT_BROM_TGT_ID), cacheable)); + IntTab(cluster(x, y), INT_BROM_TGT_ID), cacheable)); // the following segments are only defined in cluster_iob0 or in cluster_iob1 - if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) + if ( (cluster(x, y) == cluster_iob0) or (cluster(x, y) == cluster_iob1) ) { std::ostringstream siobx; siobx << "int_seg_iobx_" << x << "_" << y; maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable, config )); std::ostringstream stty; stty << "int_seg_mtty_" << x << "_" << y; maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); std::ostringstream sfbf; sfbf << "int_seg_fbuf_" << x << "_" << y; maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); std::ostringstream sbdv; sbdv << "int_seg_bdev_" << x << "_" << y; maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); std::ostringstream snic; snic << "int_seg_mnic_" << x << "_" << y; maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); std::ostringstream sdma; sdma << "int_seg_cdma_" << x << "_" << y; maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); std::ostringstream spic; spic << "int_seg_iopi_" << x << "_" << y; maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); std::ostringstream ssim; ssim << "int_seg_simh_" << x << "_" << y; maptab_int.add(Segment(ssim.str(), SEG_SIM_BASE+offset, SEG_SIM_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + IntTab(cluster(x, y), INT_IOBX_TGT_ID), not cacheable)); } @@ -602,16 +614,16 @@ // and the port index on the local interconnect. - maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), - IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); - - maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), - IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); - - maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), - IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); + maptab_int.srcid_map( IntTab( cluster(x, y), MDMA_LOCAL_SRCID ), + IntTab( cluster(x, y), INT_MDMA_INI_ID ) ); + + maptab_int.srcid_map( IntTab( cluster(x, y), IOBX_LOCAL_SRCID ), + IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); + + maptab_int.srcid_map( IntTab( cluster(x, y), IOPI_LOCAL_SRCID ), + IntTab( cluster(x, y), INT_IOBX_INI_ID ) ); for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) - maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), - IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); + maptab_int.srcid_map( IntTab( cluster(x, y), PROC_LOCAL_SRCID+p ), + IntTab( cluster(x, y), INT_PROC_INI_ID+p ) ); } } @@ -635,5 +647,5 @@ for (size_t y = 0; y < Y_SIZE ; y++) { - uint64_t offset = ((uint64_t)cluster(x,y)) + uint64_t offset = ((uint64_t)cluster(x, y)) << (vci_address_width-X_WIDTH-Y_WIDTH); @@ -641,5 +653,5 @@ sxram << "ext_seg_xram_" << x << "_" << y; maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, - SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); + SEG_RAM_SIZE, IntTab(cluster(x, y), RAM_XRAM_TGT_ID), false)); } } @@ -745,5 +757,5 @@ const bool cacheable = true; - const uint64_t offset = ((uint64_t)cluster(x,y)) + const uint64_t offset = ((uint64_t)cluster(x, y)) << (vci_address_width-X_WIDTH-Y_WIDTH); @@ -1018,6 +1030,6 @@ std::cout << std::endl; - const bool is_iob0 = (cluster(x,y) == cluster_iob0); - const bool is_iob1 = (cluster(x,y) == cluster_iob1); + const bool is_iob0 = (cluster(x, y) == cluster_iob0); + const bool is_iob1 = (cluster(x, y) == cluster_iob1); const bool is_io_cluster = is_iob0 || is_iob1; @@ -1090,6 +1102,6 @@ frozen_cycles, debug_from, - debug_ok and (cluster(x,y) == debug_memc_id), - debug_ok and (cluster(x,y) == debug_proc_id), + debug_ok and (cluster(x, y) == debug_memc_id), + debug_ok and (cluster(x, y) == (debug_proc_id >> P_WIDTH)), debug_ok and debug_iob ); @@ -1102,4 +1114,12 @@ } #endif + + // disable all interfaces of the faulty router + if (faulty_router_id != 0xFFFFFFFF) + { + int faulty_x = faulty_router_id >> Y_WIDTH; + int faulty_y = faulty_router_id & ((1 << Y_WIDTH) - 1); + clusters[faulty_x][faulty_y]->int_router_cmd[0]->set_disable_mask(0x1F); + } std::cout << std::endl; @@ -1414,5 +1434,5 @@ // simulation loop - struct timeval t1,t2; + struct timeval t1, t2; // cycles between stats @@ -1457,8 +1477,8 @@ if ( debug_proc_id != 0xFFFFFFFF ) { - size_t l = debug_proc_id % NB_PROCS_MAX ; - size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; - size_t x = cluster_xy >> 4; - size_t y = cluster_xy & 0xF; + size_t l = debug_proc_id & ((1 << P_WIDTH) - 1); + size_t cluster_xy = debug_proc_id >> P_WIDTH ; + size_t x = cluster_xy >> Y_WIDTH; + size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); clusters[x][y]->proc[l]->print_trace(1); @@ -1485,6 +1505,6 @@ if ( debug_memc_id != 0xFFFFFFFF ) { - size_t x = debug_memc_id >> 4; - size_t y = debug_memc_id & 0xF; + size_t x = debug_memc_id >> Y_WIDTH; + size_t y = debug_memc_id & ((1 << Y_WIDTH) - 1); clusters[x][y]->memc->print_trace(0); @@ -1506,6 +1526,6 @@ if ( debug_xram_id != 0xFFFFFFFF ) { - size_t x = debug_xram_id >> 4; - size_t y = debug_xram_id & 0xF; + size_t x = debug_xram_id >> Y_WIDTH; + size_t y = debug_xram_id & ((1 << Y_WIDTH) - 1); clusters[x][y]->xram->print_trace(); Index: /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 854) +++ /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 855) @@ -78,8 +78,8 @@ dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), - Uses('caba:dspin_router', + Uses('caba:reconf:dspin_router', flit_width = parameter.Reference('dspin_int_cmd_width')), - Uses('caba:dspin_router', + Uses('caba:reconf:dspin_router', flit_width = parameter.Reference('dspin_int_rsp_width')), @@ -95,8 +95,8 @@ dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), - Uses('caba:dspin_router', + Uses('caba:reconf:dspin_router', flit_width = parameter.Reference('dspin_ram_cmd_width')), - Uses('caba:dspin_router', + Uses('caba:reconf:dspin_router', flit_width = parameter.Reference('dspin_ram_rsp_width')),