- Timestamp:
- Oct 27, 2014, 12:29:14 PM (10 years ago)
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branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r861 r862 25 25 * SOCLIB_LGPL_HEADER_END 26 26 * 27 * Maintainers: alain.greiner@lip6.fr 27 * Maintainers: alain.greiner@lip6.fr 28 28 * eric.guthmuller@polytechnique.edu 29 29 * cesar.fuguet-tortolero@lip6.fr … … 62 62 using namespace sc_core; 63 63 64 template<typename vci_param_int, 64 template<typename vci_param_int, 65 65 typename vci_param_ext, 66 66 size_t memc_dspin_in_width, … … 395 395 }; 396 396 397 // debug variables 397 // debug variables 398 398 bool m_debug; 399 399 bool m_debug_previous_valid; … … 475 475 476 476 #if MONITOR_MEMCACHE_FSM == 1 477 sc_out<int> p_read_fsm; 478 sc_out<int> p_write_fsm; 479 sc_out<int> p_xram_rsp_fsm; 480 sc_out<int> p_cas_fsm; 481 sc_out<int> p_cleanup_fsm; 482 sc_out<int> p_config_fsm; 483 sc_out<int> p_alloc_heap_fsm; 484 sc_out<int> p_alloc_dir_fsm; 485 sc_out<int> p_alloc_trt_fsm; 486 sc_out<int> p_alloc_upt_fsm; 487 sc_out<int> p_alloc_ivt_fsm; 488 sc_out<int> p_tgt_cmd_fsm; 489 sc_out<int> p_tgt_rsp_fsm; 490 sc_out<int> p_ixr_cmd_fsm; 491 sc_out<int> p_ixr_rsp_fsm; 492 sc_out<int> p_cc_send_fsm; 493 sc_out<int> p_cc_receive_fsm; 494 sc_out<int> p_multi_ack_fsm; 477 sc_out<int> p_read_fsm; 478 sc_out<int> p_write_fsm; 479 sc_out<int> p_xram_rsp_fsm; 480 sc_out<int> p_cas_fsm; 481 sc_out<int> p_cleanup_fsm; 482 sc_out<int> p_config_fsm; 483 sc_out<int> p_alloc_heap_fsm; 484 sc_out<int> p_alloc_dir_fsm; 485 sc_out<int> p_alloc_trt_fsm; 486 sc_out<int> p_alloc_upt_fsm; 487 sc_out<int> p_alloc_ivt_fsm; 488 sc_out<int> p_tgt_cmd_fsm; 489 sc_out<int> p_tgt_rsp_fsm; 490 sc_out<int> p_ixr_cmd_fsm; 491 sc_out<int> p_ixr_rsp_fsm; 492 sc_out<int> p_cc_send_fsm; 493 sc_out<int> p_cc_receive_fsm; 494 sc_out<int> p_multi_ack_fsm; 495 495 #endif 496 496 … … 508 508 const size_t max_copies, // max number of copies 509 509 const size_t heap_size=HEAP_ENTRIES, 510 const size_t trt_lines=TRT_ENTRIES, 511 const size_t upt_lines=UPT_ENTRIES, 512 const size_t ivt_lines=IVT_ENTRIES, 510 const size_t trt_lines=TRT_ENTRIES, 511 const size_t upt_lines=UPT_ENTRIES, 512 const size_t ivt_lines=IVT_ENTRIES, 513 513 const size_t debug_start_cycle=0, 514 514 const bool debug_ok=false ); … … 534 534 535 535 // Component attributes 536 std::list<soclib::common::Segment> m_seglist; // segments allocated 536 std::list<soclib::common::Segment> m_seglist; // segments allocated 537 537 size_t m_nseg; // number of segments 538 538 soclib::common::Segment **m_seg; // array of segments pointers … … 607 607 // Fifo between CC_RECEIVE fsm and CLEANUP fsm 608 608 GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo; 609 609 610 610 // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm 611 611 GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo; … … 636 636 sc_signal<int> r_config_fsm; // FSM state 637 637 sc_signal<bool> r_config_lock; // lock protecting exclusive access 638 sc_signal<int> r_config_cmd; // config request type 638 sc_signal<int> r_config_cmd; // config request type 639 639 sc_signal<addr_t> r_config_address; // target buffer physical address 640 640 sc_signal<size_t> r_config_srcid; // config request srcid … … 652 652 sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP 653 653 sc_signal<size_t> r_config_trt_index; // selected entry in TRT 654 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 654 sc_signal<size_t> r_config_ivt_index; // selected entry in IVT 655 655 656 656 // Buffer between CONFIG fsm and IXR_CMD fsm … … 694 694 sc_signal<addr_t> r_read_ll_key; // LL key from llsc_global_table 695 695 696 // Buffer between READ fsm and IXR_CMD fsm 696 // Buffer between READ fsm and IXR_CMD fsm 697 697 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 698 698 sc_signal<size_t> r_read_to_ixr_cmd_index; // TRT index … … 746 746 sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed 747 747 748 // Buffer between WRITE fsm and IXR_CMD fsm 748 // Buffer between WRITE fsm and IXR_CMD fsm 749 749 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 750 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 750 sc_signal<size_t> r_write_to_ixr_cmd_index; // TRT index 751 751 752 752 // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) … … 849 849 sc_signal<data_t> * r_cas_data; // cache line data 850 850 851 // Buffer between CAS fsm and IXR_CMD fsm 851 // Buffer between CAS fsm and IXR_CMD fsm 852 852 sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request 853 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 853 sc_signal<size_t> r_cas_to_ixr_cmd_index; // TRT index 854 854 855 855 // Buffer between CAS fsm and TGT_RSP fsm … … 881 881 882 882 // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) 883 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 883 sc_signal<bool> r_ixr_rsp_to_config_ack; // one single bit 884 884 885 885 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) … … 931 931 GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids 932 932 933 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 933 // Buffer between XRAM_RSP fsm and IXR_CMD fsm 934 934 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request 935 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 935 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_index; // TRT index 936 936 937 937 //////////////////////////////////////////////////// … … 941 941 sc_signal<int> r_ixr_cmd_fsm; 942 942 sc_signal<size_t> r_ixr_cmd_word; // word index for a put 943 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 943 sc_signal<size_t> r_ixr_cmd_trdid; // TRT index value 944 944 sc_signal<addr_t> r_ixr_cmd_address; // address to XRAM 945 945 sc_signal<data_t> * r_ixr_cmd_wdata; // cache line buffer
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