Ignore:
Timestamp:
Oct 27, 2014, 12:29:15 PM (10 years ago)
Author:
cfuguet
Message:

reconf: introducing the CC_TEST FSM in the vci_mem_cache

  • This FSM receives commands from the CC_RECEIVE FSM and acknowledge them through the CLEANUP and CC_SEND FSM.
  • This commit is incomplete. The communication between the CC_TEST FSM and the CLEANUP and CC_SEND FSMs is not completely implemented.
Location:
branches/reconfiguration/modules/vci_mem_cache/caba
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • branches/reconfiguration/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd

    r861 r865  
    4040            Uses('caba:generic_fifo'),
    4141            Uses('caba:generic_llsc_global_table'),
    42             Uses('caba:dspin_dhccp_param')
     42            Uses('caba:reconf:dspin_dhccp_param')
    4343        ],
    4444

  • branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

    r862 r865  
    108108      };
    109109
     110      /* States of the CC_TEST fsm */
     111      enum cc_test_fsm_state_e
     112      {
     113        CC_TEST_IDLE,
     114        CC_TEST_SEND,
     115        CC_TEST_WAIT
     116      };
     117
    110118      /* States of the DSPIN_TGT fsm */
    111119      enum cc_receive_fsm_state_e
    … …  
    114122        CC_RECEIVE_CLEANUP,
    115123        CC_RECEIVE_CLEANUP_EOP,
    116         CC_RECEIVE_MULTI_ACK
     124        CC_RECEIVE_MULTI_ACK,
     125        CC_RECEIVE_TEST,
     126        CC_RECEIVE_TEST_EOP
    117127      };
    118128
    … …  
    611621      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
    612622
     623      // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
     624      GenericFifo<uint64_t>  m_cc_receive_to_cc_test_fifo;
     625
    613626      // Buffer between TGT_CMD fsm and TGT_RSP fsm
    614627      // (segmentation violation response request)
    … …  
    969982
    970983      ////////////////////////////////////////////////////
     984      // Registers controlled by CC_TEST fsm
     985      ////////////////////////////////////////////////////
     986
     987      sc_signal<int>      r_cc_test_fsm;
     988
     989      // Buffer between CC_TEST fsm and CC_SEND fsm
     990      sc_signal<bool>     r_cc_test_to_cc_send_req;
     991
     992      // Buffer between CC_TEST fsm and CLEANUP fsm
     993      sc_signal<bool>     r_cc_test_to_cleanup_req;
     994
     995      ////////////////////////////////////////////////////
    971996      // Registers controlled by ALLOC_DIR fsm
    972997      ////////////////////////////////////////////////////

  • branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

    r861 r865  
    5555#define DEBUG_MEMC_TGT_RSP   1 // detailed trace of TGT_RSP FSM
    5656#define DEBUG_MEMC_CLEANUP   1 // detailed trace of CLEANUP FSM
     57#define DEBUG_MEMC_CC_TEST   1 // detailed trace of CC_TEST FSM
    5758
    5859#define RANDOMIZE_CAS        1
    … …  
    9394        "CC_RECEIVE_CLEANUP",
    9495        "CC_RECEIVE_CLEANUP_EOP",
    95         "CC_RECEIVE_MULTI_ACK"
     96        "CC_RECEIVE_MULTI_ACK",
     97        "CC_RECEIVE_TEST",
     98        "CC_RECEIVE_TEST_EOP"
    9699    };
    97100    const char *cc_send_fsm_str[] =
    … …  
    120123        "CC_SEND_CONFIG_BRDCAST_HEADER",
    121124        "CC_SEND_CONFIG_BRDCAST_NLINE"
     125    };
     126    const char *cc_test_fsm_str[] =
     127    {
     128        "CC_TEST_IDLE",
     129        "CC_TEST_SEND",
     130        "CC_TEST_WAIT"
    122131    };
    123132    const char *multi_ack_fsm_str[] =
    … …  
    425434        m_cc_receive_to_cleanup_fifo("m_cc_receive_to_cleanup_fifo", 4),
    426435        m_cc_receive_to_multi_ack_fifo("m_cc_receive_to_multi_ack_fifo", 4),
     436        m_cc_receive_to_cc_test_fifo("m_cc_receive_to_cc_test_fifo", 2),
    427437
    428438        r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
    … …  
    461471        r_cc_send_fsm("r_cc_send_fsm"),
    462472        r_cc_receive_fsm("r_cc_receive_fsm"),
     473        r_cc_test_fsm("r_cc_test_fsm"),
    463474
    464475        r_alloc_dir_fsm("r_alloc_dir_fsm"),
    … …  
    810821        std::cout << "  "  << cc_send_fsm_str[r_cc_send_fsm.read()]
    811822            << " | " << cc_receive_fsm_str[r_cc_receive_fsm.read()]
     823            << " | " << cc_test_fsm_str[r_cc_test_fsm.read()]
    812824            << " | " << multi_ack_fsm_str[r_multi_ack_fsm.read()]
    813825            << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()]
    … …  
    10101022            r_cc_send_fsm    = CC_SEND_XRAM_RSP_IDLE;
    10111023            r_cc_receive_fsm = CC_RECEIVE_IDLE;
     1024            r_cc_test_fsm    = CC_TEST_IDLE;
    10121025            r_multi_ack_fsm  = MULTI_ACK_IDLE;
    10131026            r_read_fsm       = READ_IDLE;
    … …  
    10851098            m_cc_receive_to_multi_ack_fifo.init();
    10861099
     1100            m_cc_receive_to_cc_test_fifo.init();
     1101            r_cc_test_to_cc_send_req      = false;
     1102            r_cc_test_to_cleanup_req      = false;
     1103
    10871104            r_cas_to_tgt_rsp_req          = false;
    10881105            r_cas_cpt                     = 0    ;
    … …  
    11851202        bool   cc_receive_to_multi_ack_fifo_get = false;
    11861203        bool   cc_receive_to_multi_ack_fifo_put = false;
     1204
     1205        bool   cc_receive_to_cc_test_fifo_get = false;
     1206        bool   cc_receive_to_cc_test_fifo_put = false;
    11871207
    11881208        bool   write_to_cc_send_fifo_put   = false;
    … …  
    12231243                << " - CC_SEND FSM  = "    << cc_send_fsm_str[r_cc_send_fsm.read()]       << std::endl
    12241244                << " - CC_RECEIVE FSM  = " << cc_receive_fsm_str[r_cc_receive_fsm.read()] << std::endl
     1245                << " - CC_TEST FSM    = "  << cc_test_fsm_str[r_cc_test_fsm.read()]       << std::endl
    12251246                << " - MULTI_ACK FSM  = "  << multi_ack_fsm_str[r_multi_ack_fsm.read()]   << std::endl
    12261247                << " - READ FSM       = "  << read_fsm_str[r_read_fsm.read()]             << std::endl
    … …  
    66446665        } // end switch r_cas_fsm
    66456666
     6667        //////////////////////////////////////////////////////////////////////////////
     6668        //    CC_TEST FSM
     6669        //////////////////////////////////////////////////////////////////////////////
     6670        // It receives test command from the CC_RECEIVE FSM and initiates test
     6671        // commands to the CC_SEND and CC_CLEANUP FSMs.
     6672        //
     6673        // This automate is used during the fault-tolerance reconfiguration procedure
     6674        // to test the coherence network: M2P, P2M and CLACK sub-networks.
     6675        //
     6676        // Test transactions are initiated by L1 caches which sends a test command
     6677        // through the P2M channel. Target memory cache acknowledges this test
     6678        // command by sending two responses: one through the M2P and the other
     6679        // through the CLACK sub-networks.
     6680        //
     6681        // A P2M test packet contains two flits: the first one is the header and the
     6682        // second one contains the signature to copy in the M2P and CLACK test
     6683        // packets. To avoid adding two more registers to this test FSM, the second
     6684        // flit is directly copied from the CC_RECEIVE to CC_TEST FIFO by the CC_SEND
     6685        // and CLEANUP FSMs. Consequently, this second flit is consumed by this FSM
     6686        // when the CC_SEND and CLEANUP FSMs acknowledge the send request.
     6687        //////////////////////////////////////////////////////////////////////////////
     6688        switch (r_cc_test_fsm.read())
     6689        {
     6690            case CC_TEST_IDLE:
     6691                if (not m_cc_receive_to_cc_test_fifo.rok()) break;
     6692
     6693                cc_receive_to_cc_test_fifo_get = true;
     6694                r_cc_test_fsm = CC_TEST_SEND;
     6695                break;
     6696
     6697            case CC_TEST_SEND:
     6698                assert(not r_cc_test_to_cc_send_req.read() and
     6699                       not r_cc_test_to_cleanup_req.read());
     6700
     6701                r_cc_test_to_cc_send_req = true;
     6702                r_cc_test_to_cleanup_req = true;
     6703                r_cc_test_fsm = CC_TEST_WAIT;
     6704                break;
     6705
     6706            case CC_TEST_WAIT:
     6707                if (r_cc_test_to_cc_send_req.read() or
     6708                    r_cc_test_to_cleanup_req.read())
     6709                {
     6710                    // TODO:
     6711                    // When a timeout exception is triggered:
     6712                    //  1. go to IDLE
     6713                    //  2. consume the test flit from the FIFO
     6714                    break;
     6715                }
     6716
     6717                cc_receive_to_cc_test_fifo_get = true;
     6718                r_cc_test_fsm = CC_TEST_IDLE;
     6719                break;
     6720        } // end switch r_cc_test_fsm
    66466721
    66476722        //////////////////////////////////////////////////////////////////////////////
    … …  
    72437318                            DspinDhccpParam::P2M_TYPE);
    72447319
     7320                uint8_t test =
     7321                    DspinDhccpParam::dspin_get(
     7322                            p_dspin_p2m.data.read(),
     7323                            DspinDhccpParam::P2M_TEST);
     7324
     7325                if ((type == DspinDhccpParam::TYPE_TEST) and (test == 1))
     7326                {
     7327                    r_cc_receive_fsm = CC_RECEIVE_TEST;
     7328                    break;
     7329                }
     7330
    72457331                if ((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or
    72467332                        (type == DspinDhccpParam::TYPE_CLEANUP_INST))
    … …  
    73287414                cc_receive_to_multi_ack_fifo_put = true;
    73297415                r_cc_receive_fsm = CC_RECEIVE_IDLE;
     7416                break;
     7417            }
     7418            ////////////////////////
     7419            case CC_RECEIVE_TEST:
     7420            {
     7421                // write first flit in CC_RECEIVE to CC_TEST fifo
     7422
     7423                if (not p_dspin_p2m.write or not m_cc_receive_to_cc_test_fifo.wok())
     7424                    break;
     7425
     7426                assert(not p_dspin_p2m.eop.read() and
     7427                       "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
     7428                       "TEST command must have two flits");
     7429
     7430                cc_receive_to_cc_test_fifo_put = true;
     7431                r_cc_receive_fsm               = CC_RECEIVE_TEST_EOP;
     7432                break;
     7433            }
     7434            ////////////////////////
     7435            case CC_RECEIVE_TEST_EOP:
     7436            {
     7437                // write second flit in CC_RECEIVE to CC_TEST fifo
     7438
     7439                if (not p_dspin_p2m.write or not m_cc_receive_to_cc_test_fifo.wok())
     7440                    break;
     7441
     7442                assert(p_dspin_p2m.eop.read() and
     7443                        "VCI_MEM_CACHE ERROR in CC_RECEIVE : "
     7444                        "TEST command must have two flits");
     7445
     7446                cc_receive_to_cc_test_fifo_put = true;
     7447                r_cc_receive_fsm               = CC_RECEIVE_IDLE;
    73307448                break;
    73317449            }
    … …  
    85858703        m_cc_receive_to_multi_ack_fifo.update(cc_receive_to_multi_ack_fifo_get,
    85868704                cc_receive_to_multi_ack_fifo_put,
     8705                p_dspin_p2m.data.read());
     8706
     8707        ////////////////////////////////////////////////////////////////////////////////////
     8708        //    CC_RECEIVE to CC_TEST FIFO
     8709        ////////////////////////////////////////////////////////////////////////////////////
     8710
     8711        m_cc_receive_to_cc_test_fifo.update(cc_receive_to_cc_test_fifo_get,
     8712                cc_receive_to_cc_test_fifo_put,
    85878713                p_dspin_p2m.data.read());
    85888714
    … …  
    93989524                break;
    93999525            }
     9526            case CC_RECEIVE_TEST:
     9527            case CC_RECEIVE_TEST_EOP:
     9528            {
     9529                p_dspin_p2m.read = m_cc_receive_to_cc_test_fifo.wok();
     9530                break;
     9531            }
    94009532        }
    94019533        // end switch r_cc_send_fsm
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