Index: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd =================================================================== --- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd (revision 864) +++ branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd (revision 865) @@ -32,5 +32,5 @@ parameter.Reference('addr_size')) ), - Uses('caba:dspin_dhccp_param'), + Uses('caba:reconf:dspin_dhccp_param'), ], Index: branches/reconfiguration/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- branches/reconfiguration/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 864) +++ branches/reconfiguration/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 865) @@ -40,5 +40,5 @@ Uses('caba:generic_fifo'), Uses('caba:generic_llsc_global_table'), - Uses('caba:dspin_dhccp_param') + Uses('caba:reconf:dspin_dhccp_param') ], Index: branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 864) +++ branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 865) @@ -108,4 +108,12 @@ }; + /* States of the CC_TEST fsm */ + enum cc_test_fsm_state_e + { + CC_TEST_IDLE, + CC_TEST_SEND, + CC_TEST_WAIT + }; + /* States of the DSPIN_TGT fsm */ enum cc_receive_fsm_state_e @@ -114,5 +122,7 @@ CC_RECEIVE_CLEANUP, CC_RECEIVE_CLEANUP_EOP, - CC_RECEIVE_MULTI_ACK + CC_RECEIVE_MULTI_ACK, + CC_RECEIVE_TEST, + CC_RECEIVE_TEST_EOP }; @@ -611,4 +621,7 @@ GenericFifo m_cc_receive_to_multi_ack_fifo; + // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm + GenericFifo m_cc_receive_to_cc_test_fifo; + // Buffer between TGT_CMD fsm and TGT_RSP fsm // (segmentation violation response request) @@ -969,4 +982,16 @@ //////////////////////////////////////////////////// + // Registers controlled by CC_TEST fsm + //////////////////////////////////////////////////// + + sc_signal r_cc_test_fsm; + + // Buffer between CC_TEST fsm and CC_SEND fsm + sc_signal r_cc_test_to_cc_send_req; + + // Buffer between CC_TEST fsm and CLEANUP fsm + sc_signal r_cc_test_to_cleanup_req; + + //////////////////////////////////////////////////// // Registers controlled by ALLOC_DIR fsm //////////////////////////////////////////////////// Index: branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 864) +++ branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 865) @@ -55,4 +55,5 @@ #define DEBUG_MEMC_TGT_RSP 1 // detailed trace of TGT_RSP FSM #define DEBUG_MEMC_CLEANUP 1 // detailed trace of CLEANUP FSM +#define DEBUG_MEMC_CC_TEST 1 // detailed trace of CC_TEST FSM #define RANDOMIZE_CAS 1 @@ -93,5 +94,7 @@ "CC_RECEIVE_CLEANUP", "CC_RECEIVE_CLEANUP_EOP", - "CC_RECEIVE_MULTI_ACK" + "CC_RECEIVE_MULTI_ACK", + "CC_RECEIVE_TEST", + "CC_RECEIVE_TEST_EOP" }; const char *cc_send_fsm_str[] = @@ -120,4 +123,10 @@ "CC_SEND_CONFIG_BRDCAST_HEADER", "CC_SEND_CONFIG_BRDCAST_NLINE" + }; + const char *cc_test_fsm_str[] = + { + "CC_TEST_IDLE", + "CC_TEST_SEND", + "CC_TEST_WAIT" }; const char *multi_ack_fsm_str[] = @@ -425,4 +434,5 @@ m_cc_receive_to_cleanup_fifo("m_cc_receive_to_cleanup_fifo", 4), m_cc_receive_to_multi_ack_fifo("m_cc_receive_to_multi_ack_fifo", 4), + m_cc_receive_to_cc_test_fifo("m_cc_receive_to_cc_test_fifo", 2), r_tgt_cmd_fsm("r_tgt_cmd_fsm"), @@ -461,4 +471,5 @@ r_cc_send_fsm("r_cc_send_fsm"), r_cc_receive_fsm("r_cc_receive_fsm"), + r_cc_test_fsm("r_cc_test_fsm"), r_alloc_dir_fsm("r_alloc_dir_fsm"), @@ -810,4 +821,5 @@ std::cout << " " << cc_send_fsm_str[r_cc_send_fsm.read()] << " | " << cc_receive_fsm_str[r_cc_receive_fsm.read()] + << " | " << cc_test_fsm_str[r_cc_test_fsm.read()] << " | " << multi_ack_fsm_str[r_multi_ack_fsm.read()] << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] @@ -1010,4 +1022,5 @@ r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; r_cc_receive_fsm = CC_RECEIVE_IDLE; + r_cc_test_fsm = CC_TEST_IDLE; r_multi_ack_fsm = MULTI_ACK_IDLE; r_read_fsm = READ_IDLE; @@ -1085,4 +1098,8 @@ m_cc_receive_to_multi_ack_fifo.init(); + m_cc_receive_to_cc_test_fifo.init(); + r_cc_test_to_cc_send_req = false; + r_cc_test_to_cleanup_req = false; + r_cas_to_tgt_rsp_req = false; r_cas_cpt = 0 ; @@ -1185,4 +1202,7 @@ bool cc_receive_to_multi_ack_fifo_get = false; bool cc_receive_to_multi_ack_fifo_put = false; + + bool cc_receive_to_cc_test_fifo_get = false; + bool cc_receive_to_cc_test_fifo_put = false; bool write_to_cc_send_fifo_put = false; @@ -1223,4 +1243,5 @@ << " - CC_SEND FSM = " << cc_send_fsm_str[r_cc_send_fsm.read()] << std::endl << " - CC_RECEIVE FSM = " << cc_receive_fsm_str[r_cc_receive_fsm.read()] << std::endl + << " - CC_TEST FSM = " << cc_test_fsm_str[r_cc_test_fsm.read()] << std::endl << " - MULTI_ACK FSM = " << multi_ack_fsm_str[r_multi_ack_fsm.read()] << std::endl << " - READ FSM = " << read_fsm_str[r_read_fsm.read()] << std::endl @@ -6644,4 +6665,58 @@ } // end switch r_cas_fsm + ////////////////////////////////////////////////////////////////////////////// + // CC_TEST FSM + ////////////////////////////////////////////////////////////////////////////// + // It receives test command from the CC_RECEIVE FSM and initiates test + // commands to the CC_SEND and CC_CLEANUP FSMs. + // + // This automate is used during the fault-tolerance reconfiguration procedure + // to test the coherence network: M2P, P2M and CLACK sub-networks. + // + // Test transactions are initiated by L1 caches which sends a test command + // through the P2M channel. Target memory cache acknowledges this test + // command by sending two responses: one through the M2P and the other + // through the CLACK sub-networks. + // + // A P2M test packet contains two flits: the first one is the header and the + // second one contains the signature to copy in the M2P and CLACK test + // packets. To avoid adding two more registers to this test FSM, the second + // flit is directly copied from the CC_RECEIVE to CC_TEST FIFO by the CC_SEND + // and CLEANUP FSMs. Consequently, this second flit is consumed by this FSM + // when the CC_SEND and CLEANUP FSMs acknowledge the send request. + ////////////////////////////////////////////////////////////////////////////// + switch (r_cc_test_fsm.read()) + { + case CC_TEST_IDLE: + if (not m_cc_receive_to_cc_test_fifo.rok()) break; + + cc_receive_to_cc_test_fifo_get = true; + r_cc_test_fsm = CC_TEST_SEND; + break; + + case CC_TEST_SEND: + assert(not r_cc_test_to_cc_send_req.read() and + not r_cc_test_to_cleanup_req.read()); + + r_cc_test_to_cc_send_req = true; + r_cc_test_to_cleanup_req = true; + r_cc_test_fsm = CC_TEST_WAIT; + break; + + case CC_TEST_WAIT: + if (r_cc_test_to_cc_send_req.read() or + r_cc_test_to_cleanup_req.read()) + { + // TODO: + // When a timeout exception is triggered: + // 1. go to IDLE + // 2. consume the test flit from the FIFO + break; + } + + cc_receive_to_cc_test_fifo_get = true; + r_cc_test_fsm = CC_TEST_IDLE; + break; + } // end switch r_cc_test_fsm ////////////////////////////////////////////////////////////////////////////// @@ -7243,4 +7318,15 @@ DspinDhccpParam::P2M_TYPE); + uint8_t test = + DspinDhccpParam::dspin_get( + p_dspin_p2m.data.read(), + DspinDhccpParam::P2M_TEST); + + if ((type == DspinDhccpParam::TYPE_TEST) and (test == 1)) + { + r_cc_receive_fsm = CC_RECEIVE_TEST; + break; + } + if ((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or (type == DspinDhccpParam::TYPE_CLEANUP_INST)) @@ -7328,4 +7414,36 @@ cc_receive_to_multi_ack_fifo_put = true; r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + //////////////////////// + case CC_RECEIVE_TEST: + { + // write first flit in CC_RECEIVE to CC_TEST fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cc_test_fifo.wok()) + break; + + assert(not p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "TEST command must have two flits"); + + cc_receive_to_cc_test_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_TEST_EOP; + break; + } + //////////////////////// + case CC_RECEIVE_TEST_EOP: + { + // write second flit in CC_RECEIVE to CC_TEST fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cc_test_fifo.wok()) + break; + + assert(p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "TEST command must have two flits"); + + cc_receive_to_cc_test_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; break; } @@ -8585,4 +8703,12 @@ m_cc_receive_to_multi_ack_fifo.update(cc_receive_to_multi_ack_fifo_get, cc_receive_to_multi_ack_fifo_put, + p_dspin_p2m.data.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE to CC_TEST FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cc_receive_to_cc_test_fifo.update(cc_receive_to_cc_test_fifo_get, + cc_receive_to_cc_test_fifo_put, p_dspin_p2m.data.read()); @@ -9398,4 +9524,10 @@ break; } + case CC_RECEIVE_TEST: + case CC_RECEIVE_TEST_EOP: + { + p_dspin_p2m.read = m_cc_receive_to_cc_test_fifo.wok(); + break; + } } // end switch r_cc_send_fsm Index: branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf =================================================================== --- branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf (revision 864) +++ branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf (revision 865) @@ -10,5 +10,5 @@ tsarpath = environ['TSARPATH'] config.addDescPath(join(tsarpath, "trunk/lib")) -config.addDescPath(join(tsarpath, "trunk/communication")) config.addDescPath(join(tsarpath, "trunk/modules")) +config.addDescPath(join(tsarpath, "branches/reconfiguration/communication")) config.addDescPath(join(tsarpath, "branches/reconfiguration/modules")) Index: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 864) +++ branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 865) @@ -38,5 +38,5 @@ gdb_iss_t = 'common:mips32el'), - Uses('caba:vci_mem_cache', + Uses('caba:reconf:vci_mem_cache', memc_cell_size_int = parameter.Reference('vci_data_width_int'), memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),