Changeset 868 for branches/reconfiguration/modules
- Timestamp:
- Oct 27, 2014, 5:40:47 PM (10 years ago)
- Location:
- branches/reconfiguration/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r865 r868 134 134 CC_SEND_CAS_IDLE, 135 135 CC_SEND_CONFIG_IDLE, 136 CC_SEND_TEST_IDLE, 136 137 CC_SEND_XRAM_RSP_BRDCAST_HEADER, 137 138 CC_SEND_XRAM_RSP_BRDCAST_NLINE, … … 152 153 CC_SEND_CONFIG_INVAL_NLINE, 153 154 CC_SEND_CONFIG_BRDCAST_HEADER, 154 CC_SEND_CONFIG_BRDCAST_NLINE 155 CC_SEND_CONFIG_BRDCAST_NLINE, 156 CC_SEND_TEST_HEADER, 157 CC_SEND_TEST_SIGNATURE 155 158 }; 156 159 … … 986 989 987 990 sc_signal<int> r_cc_test_fsm; 991 sc_signal<size_t> r_cc_test_srcid; 988 992 989 993 // Buffer between CC_TEST fsm and CC_SEND fsm -
branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r865 r868 104 104 "CC_SEND_CAS_IDLE", 105 105 "CC_SEND_CONFIG_IDLE", 106 "CC_SEND_TEST_IDLE", 106 107 "CC_SEND_XRAM_RSP_BRDCAST_HEADER", 107 108 "CC_SEND_XRAM_RSP_BRDCAST_NLINE", … … 122 123 "CC_SEND_CONFIG_INVAL_NLINE", 123 124 "CC_SEND_CONFIG_BRDCAST_HEADER", 124 "CC_SEND_CONFIG_BRDCAST_NLINE" 125 "CC_SEND_CONFIG_BRDCAST_NLINE", 126 "CC_SEND_TEST_HEADER", 127 "CC_SEND_TEST_SIGNATURE" 125 128 }; 126 129 const char *cc_test_fsm_str[] = … … 6689 6692 { 6690 6693 case CC_TEST_IDLE: 6694 { 6691 6695 if (not m_cc_receive_to_cc_test_fifo.rok()) break; 6692 6696 6697 uint32_t srcid = DspinDhccpParam::dspin_get( 6698 m_cc_receive_to_cc_test_fifo.read(), 6699 DspinDhccpParam::CC_TEST_SRCID); 6700 6693 6701 cc_receive_to_cc_test_fifo_get = true; 6702 r_cc_test_srcid = srcid; 6694 6703 r_cc_test_fsm = CC_TEST_SEND; 6695 6704 break; 6705 } 6696 6706 6697 6707 case CC_TEST_SEND: … … 6726 6736 // network, used to update or invalidate cache lines in L1 caches. 6727 6737 // 6728 // It implements a round-robin priority between the f ourpossible client FSMs6729 // XRAM_RSP > CAS > WRITE > CONFIG 6738 // It implements a round-robin priority between the five possible client FSMs 6739 // XRAM_RSP > CAS > WRITE > CONFIG > TEST 6730 6740 // 6731 6741 // Each FSM can request the next services: … … 6738 6748 // - r_config_to_cc_send_multi_req : multi-inval 6739 6749 // r_config_to_cc_send_brdcast_req : broadcast-inval 6750 // - r_cc_test_to_cc_send_req : test req 6740 6751 // 6741 6752 // An inval request is a double DSPIN flit command containing: … … 6746 6757 // 2. the index of the first modified word in the line. 6747 6758 // 3. the data to update 6759 // 6760 // A test request is a two-flits DSPIN packet containing: 6761 // 1. header flit with destination 6762 // 2. a test signature 6748 6763 /////////////////////////////////////////////////////////////////////////////// 6749 6764 … … 6753 6768 case CC_SEND_CONFIG_IDLE: // XRAM_RSP FSM has highest priority 6754 6769 { 6770 // CC_TEST 6771 if (r_cc_test_to_cc_send_req.read()) 6772 { 6773 r_cc_send_fsm = CC_SEND_TEST_HEADER; 6774 break; 6775 } 6755 6776 // XRAM_RSP 6756 6777 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or … … 6816 6837 break; 6817 6838 } 6839 // CC_TEST 6840 if (r_cc_test_to_cc_send_req.read()) 6841 { 6842 r_cc_send_fsm = CC_SEND_TEST_HEADER; 6843 break; 6844 } 6818 6845 // XRAM_RSP 6819 6846 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or … … 6893 6920 break; 6894 6921 } 6922 // CC_TEST 6923 if (r_cc_test_to_cc_send_req.read()) 6924 { 6925 r_cc_send_fsm = CC_SEND_TEST_HEADER; 6926 break; 6927 } 6895 6928 // XRAM_RSP 6896 6929 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or … … 6910 6943 case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority 6911 6944 { 6945 // WRITE 6912 6946 if (m_write_to_cc_send_inst_fifo.rok() or 6913 6947 r_write_to_cc_send_multi_req.read()) … … 6932 6966 break; 6933 6967 } 6968 // CC_TEST 6969 if (r_cc_test_to_cc_send_req.read()) 6970 { 6971 r_cc_send_fsm = CC_SEND_TEST_HEADER; 6972 break; 6973 } 6974 // XRAM_RSP 6934 6975 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or 6935 6976 r_xram_rsp_to_cc_send_multi_req.read()) … … 6943 6984 break; 6944 6985 } 6986 // CAS 6945 6987 if (m_cas_to_cc_send_inst_fifo.rok() or 6946 6988 r_cas_to_cc_send_multi_req.read()) … … 6952 6994 { 6953 6995 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; 6996 break; 6997 } 6998 break; 6999 } 7000 ////////////////////// 7001 case CC_SEND_TEST_IDLE: 7002 { 7003 // WRITE 7004 if (m_write_to_cc_send_inst_fifo.rok() or 7005 r_write_to_cc_send_multi_req.read()) 7006 { 7007 r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; 7008 break; 7009 } 7010 if (r_write_to_cc_send_brdcast_req.read()) 7011 { 7012 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; 7013 break; 7014 } 7015 // CONFIG 7016 if (r_config_to_cc_send_multi_req.read()) 7017 { 7018 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; 7019 break; 7020 } 7021 if (r_config_to_cc_send_brdcast_req.read()) 7022 { 7023 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; 7024 break; 7025 } 7026 // XRAM_RSP 7027 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or 7028 r_xram_rsp_to_cc_send_multi_req.read()) 7029 { 7030 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; 7031 break; 7032 } 7033 if (r_xram_rsp_to_cc_send_brdcast_req.read()) 7034 { 7035 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; 7036 break; 7037 } 7038 // CAS 7039 if (m_cas_to_cc_send_inst_fifo.rok() or 7040 r_cas_to_cc_send_multi_req.read()) 7041 { 7042 r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; 7043 break; 7044 } 7045 if (r_cas_to_cc_send_brdcast_req.read()) 7046 { 7047 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; 7048 break; 7049 } 7050 // CC_TEST 7051 if (r_cc_test_to_cc_send_req.read()) 7052 { 7053 r_cc_send_fsm = CC_SEND_TEST_HEADER; 6954 7054 break; 6955 7055 } … … 7296 7396 break; 7297 7397 } 7398 /////////////////////////////////// 7399 case CC_SEND_TEST_HEADER: // send first flit TEST (from CC_TEST FSM) 7400 { 7401 if (not p_dspin_m2p.read) break; 7402 r_cc_send_fsm = CC_SEND_TEST_SIGNATURE; 7403 break; 7404 } 7405 ////////////////////////////////// 7406 case CC_SEND_TEST_SIGNATURE: // send second flit TEST (from CC_TEST FSM) 7407 { 7408 if (not p_dspin_m2p.read) break; 7409 r_cc_test_to_cc_send_req = false; 7410 r_cc_send_fsm = CC_SEND_TEST_IDLE; 7411 break; 7412 } 7298 7413 } 7299 7414 // end switch r_cc_send_fsm … … 7321 7436 DspinDhccpParam::dspin_get( 7322 7437 p_dspin_p2m.data.read(), 7323 DspinDhccpParam:: P2M_TEST);7438 DspinDhccpParam::CC_TEST_TEST); 7324 7439 7325 7440 if ((type == DspinDhccpParam::TYPE_TEST) and (test == 1)) … … 9449 9564 break; 9450 9565 } 9566 ///////////////////////////////////// 9567 case CC_SEND_TEST_HEADER: 9568 { 9569 uint64_t flit = 0; 9570 9571 DspinDhccpParam::dspin_set(flit, 9572 r_cc_test_srcid.read(), 9573 DspinDhccpParam::CC_TEST_DEST); 9574 9575 DspinDhccpParam::dspin_set(flit, 9576 1ULL, 9577 DspinDhccpParam::CC_TEST_TEST); 9578 9579 // TODO: Send MemoryCache SRCID too ? 9580 9581 p_dspin_m2p.write = true; 9582 p_dspin_m2p.data = flit; 9583 break; 9584 } 9585 //////////////////////////////////// 9586 case CC_SEND_TEST_SIGNATURE: 9587 { 9588 uint64_t flit = 0; 9589 uint64_t data = (uint64_t)m_cc_receive_to_cc_test_fifo.read(); 9590 uint64_t lsb = (uint64_t)m_cc_receive_to_cc_test_fifo.read() & ((1 << 7) - 1); 9591 9592 DspinDhccpParam::dspin_set(flit, 9593 data | (lsb << 32), 9594 DspinDhccpParam::CC_TEST_SIGNATURE); 9595 9596 p_dspin_m2p.write = true; 9597 p_dspin_m2p.eop = true; 9598 p_dspin_m2p.data = flit; 9599 break; 9600 } 9451 9601 } 9452 9602
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