Index: branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 865) +++ branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 868) @@ -134,4 +134,5 @@ CC_SEND_CAS_IDLE, CC_SEND_CONFIG_IDLE, + CC_SEND_TEST_IDLE, CC_SEND_XRAM_RSP_BRDCAST_HEADER, CC_SEND_XRAM_RSP_BRDCAST_NLINE, @@ -152,5 +153,7 @@ CC_SEND_CONFIG_INVAL_NLINE, CC_SEND_CONFIG_BRDCAST_HEADER, - CC_SEND_CONFIG_BRDCAST_NLINE + CC_SEND_CONFIG_BRDCAST_NLINE, + CC_SEND_TEST_HEADER, + CC_SEND_TEST_SIGNATURE }; @@ -986,4 +989,5 @@ sc_signal r_cc_test_fsm; + sc_signal r_cc_test_srcid; // Buffer between CC_TEST fsm and CC_SEND fsm Index: branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 865) +++ branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 868) @@ -104,4 +104,5 @@ "CC_SEND_CAS_IDLE", "CC_SEND_CONFIG_IDLE", + "CC_SEND_TEST_IDLE", "CC_SEND_XRAM_RSP_BRDCAST_HEADER", "CC_SEND_XRAM_RSP_BRDCAST_NLINE", @@ -122,5 +123,7 @@ "CC_SEND_CONFIG_INVAL_NLINE", "CC_SEND_CONFIG_BRDCAST_HEADER", - "CC_SEND_CONFIG_BRDCAST_NLINE" + "CC_SEND_CONFIG_BRDCAST_NLINE", + "CC_SEND_TEST_HEADER", + "CC_SEND_TEST_SIGNATURE" }; const char *cc_test_fsm_str[] = @@ -6689,9 +6692,16 @@ { case CC_TEST_IDLE: + { if (not m_cc_receive_to_cc_test_fifo.rok()) break; + uint32_t srcid = DspinDhccpParam::dspin_get( + m_cc_receive_to_cc_test_fifo.read(), + DspinDhccpParam::CC_TEST_SRCID); + cc_receive_to_cc_test_fifo_get = true; + r_cc_test_srcid = srcid; r_cc_test_fsm = CC_TEST_SEND; break; + } case CC_TEST_SEND: @@ -6726,6 +6736,6 @@ // network, used to update or invalidate cache lines in L1 caches. // - // It implements a round-robin priority between the four possible client FSMs - // XRAM_RSP > CAS > WRITE > CONFIG + // It implements a round-robin priority between the five possible client FSMs + // XRAM_RSP > CAS > WRITE > CONFIG > TEST // // Each FSM can request the next services: @@ -6738,4 +6748,5 @@ // - r_config_to_cc_send_multi_req : multi-inval // r_config_to_cc_send_brdcast_req : broadcast-inval + // - r_cc_test_to_cc_send_req : test req // // An inval request is a double DSPIN flit command containing: @@ -6746,4 +6757,8 @@ // 2. the index of the first modified word in the line. // 3. the data to update + // + // A test request is a two-flits DSPIN packet containing: + // 1. header flit with destination + // 2. a test signature /////////////////////////////////////////////////////////////////////////////// @@ -6753,4 +6768,10 @@ case CC_SEND_CONFIG_IDLE: // XRAM_RSP FSM has highest priority { + // CC_TEST + if (r_cc_test_to_cc_send_req.read()) + { + r_cc_send_fsm = CC_SEND_TEST_HEADER; + break; + } // XRAM_RSP if (m_xram_rsp_to_cc_send_inst_fifo.rok() or @@ -6816,4 +6837,10 @@ break; } + // CC_TEST + if (r_cc_test_to_cc_send_req.read()) + { + r_cc_send_fsm = CC_SEND_TEST_HEADER; + break; + } // XRAM_RSP if (m_xram_rsp_to_cc_send_inst_fifo.rok() or @@ -6893,4 +6920,10 @@ break; } + // CC_TEST + if (r_cc_test_to_cc_send_req.read()) + { + r_cc_send_fsm = CC_SEND_TEST_HEADER; + break; + } // XRAM_RSP if (m_xram_rsp_to_cc_send_inst_fifo.rok() or @@ -6910,4 +6943,5 @@ case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority { + // WRITE if (m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -6932,4 +6966,11 @@ break; } + // CC_TEST + if (r_cc_test_to_cc_send_req.read()) + { + r_cc_send_fsm = CC_SEND_TEST_HEADER; + break; + } + // XRAM_RSP if (m_xram_rsp_to_cc_send_inst_fifo.rok() or r_xram_rsp_to_cc_send_multi_req.read()) @@ -6943,4 +6984,5 @@ break; } + // CAS if (m_cas_to_cc_send_inst_fifo.rok() or r_cas_to_cc_send_multi_req.read()) @@ -6952,4 +6994,62 @@ { r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + break; + } + ////////////////////// + case CC_SEND_TEST_IDLE: + { + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // CC_TEST + if (r_cc_test_to_cc_send_req.read()) + { + r_cc_send_fsm = CC_SEND_TEST_HEADER; break; } @@ -7296,4 +7396,19 @@ break; } + /////////////////////////////////// + case CC_SEND_TEST_HEADER: // send first flit TEST (from CC_TEST FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_TEST_SIGNATURE; + break; + } + ////////////////////////////////// + case CC_SEND_TEST_SIGNATURE: // send second flit TEST (from CC_TEST FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_test_to_cc_send_req = false; + r_cc_send_fsm = CC_SEND_TEST_IDLE; + break; + } } // end switch r_cc_send_fsm @@ -7321,5 +7436,5 @@ DspinDhccpParam::dspin_get( p_dspin_p2m.data.read(), - DspinDhccpParam::P2M_TEST); + DspinDhccpParam::CC_TEST_TEST); if ((type == DspinDhccpParam::TYPE_TEST) and (test == 1)) @@ -9449,4 +9564,39 @@ break; } + ///////////////////////////////////// + case CC_SEND_TEST_HEADER: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set(flit, + r_cc_test_srcid.read(), + DspinDhccpParam::CC_TEST_DEST); + + DspinDhccpParam::dspin_set(flit, + 1ULL, + DspinDhccpParam::CC_TEST_TEST); + + // TODO: Send MemoryCache SRCID too ? + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + //////////////////////////////////// + case CC_SEND_TEST_SIGNATURE: + { + uint64_t flit = 0; + uint64_t data = (uint64_t)m_cc_receive_to_cc_test_fifo.read(); + uint64_t lsb = (uint64_t)m_cc_receive_to_cc_test_fifo.read() & ((1 << 7) - 1); + + DspinDhccpParam::dspin_set(flit, + data | (lsb << 32), + DspinDhccpParam::CC_TEST_SIGNATURE); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } }