- Timestamp:
- Oct 27, 2014, 7:08:26 PM (10 years ago)
- Location:
- branches/reconfiguration/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/reconfiguration/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r868 r869 323 323 CLEANUP_IVT_CLEAR, 324 324 CLEANUP_WRITE_RSP, 325 CLEANUP_SEND_CLACK 325 CLEANUP_SEND_CLACK, 326 CLEANUP_TEST_HEADER, 327 CLEANUP_TEST_SIGNATURE 326 328 }; 327 329 -
branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r868 r869 281 281 "CLEANUP_IVT_CLEAR", 282 282 "CLEANUP_WRITE_RSP", 283 "CLEANUP_SEND_CLACK" 283 "CLEANUP_SEND_CLACK", 284 "CLEANUP_TEST_HEADER", 285 "CLEANUP_TEST_SIGNATURE" 284 286 }; 285 287 const char *alloc_dir_fsm_str[] = … … 5307 5309 case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command 5308 5310 { 5311 if (r_cc_test_to_cleanup_req.read()) 5312 { 5313 r_cleanup_fsm = CLEANUP_TEST_HEADER; 5314 break; 5315 } 5316 5309 5317 if (not m_cc_receive_to_cleanup_fifo.rok()) break; 5310 5318 … … 5341 5349 } 5342 5350 #endif 5351 break; 5352 } 5353 /////////////////////// 5354 case CLEANUP_TEST_HEADER: 5355 { 5356 if (not p_dspin_clack.read) break; 5357 r_cleanup_fsm = CLEANUP_TEST_SIGNATURE; 5358 break; 5359 } 5360 /////////////////////// 5361 case CLEANUP_TEST_SIGNATURE: 5362 { 5363 if (not p_dspin_clack.read) break; 5364 r_cc_test_to_cleanup_req = false; 5365 r_cleanup_fsm = CLEANUP_IDLE; 5343 5366 break; 5344 5367 } … … 6697 6720 uint32_t srcid = DspinDhccpParam::dspin_get( 6698 6721 m_cc_receive_to_cc_test_fifo.read(), 6699 DspinDhccpParam:: CC_TEST_SRCID);6722 DspinDhccpParam::TEST_P2M_SRCID); 6700 6723 6701 6724 cc_receive_to_cc_test_fifo_get = true; … … 7436 7459 DspinDhccpParam::dspin_get( 7437 7460 p_dspin_p2m.data.read(), 7438 DspinDhccpParam::CC_TEST_TEST); 7439 7440 if ((type == DspinDhccpParam::TYPE_TEST) and (test == 1)) 7461 DspinDhccpParam::TEST_P2M_TEST); 7462 7463 // TODO: verify DEST field 7464 7465 if ((type == DspinDhccpParam::TYPE_TEST) and test) 7441 7466 { 7442 7467 r_cc_receive_fsm = CC_RECEIVE_TEST; … … 9571 9596 DspinDhccpParam::dspin_set(flit, 9572 9597 r_cc_test_srcid.read(), 9573 DspinDhccpParam:: CC_TEST_DEST);9598 DspinDhccpParam::TEST_M2P_DEST); 9574 9599 9575 9600 DspinDhccpParam::dspin_set(flit, 9576 9601 1ULL, 9577 DspinDhccpParam:: CC_TEST_TEST);9602 DspinDhccpParam::TEST_M2P_TEST); 9578 9603 9579 9604 // TODO: Send MemoryCache SRCID too ? … … 9586 9611 case CC_SEND_TEST_SIGNATURE: 9587 9612 { 9613 uint64_t data = 9614 DspinDhccpParam::dspin_get( 9615 m_cc_receive_to_cc_test_fifo.read(), 9616 DspinDhccpParam::TEST_P2M_SIGNATURE); 9617 9618 uint64_t lsb = (uint64_t)data & ((1 << 7) - 1); 9588 9619 uint64_t flit = 0; 9589 uint64_t data = (uint64_t)m_cc_receive_to_cc_test_fifo.read();9590 uint64_t lsb = (uint64_t)m_cc_receive_to_cc_test_fifo.read() & ((1 << 7) - 1);9591 9592 9620 DspinDhccpParam::dspin_set(flit, 9593 9621 data | (lsb << 32), 9594 DspinDhccpParam:: CC_TEST_SIGNATURE);9622 DspinDhccpParam::TEST_M2P_SIGNATURE); 9595 9623 9596 9624 p_dspin_m2p.write = true; … … 9605 9633 //////////////////////////////////////////////////////////////////// 9606 9634 9607 if (r_cleanup_fsm.read() == CLEANUP_SEND_CLACK)9635 switch(r_cleanup_fsm.read()) 9608 9636 { 9609 uint8_t cleanup_ack_type; 9610 if (r_cleanup_inst.read()) 9611 { 9612 cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; 9613 } 9614 else 9615 { 9616 cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; 9617 } 9618 9619 uint64_t flit = 0; 9620 uint64_t dest = r_cleanup_srcid.read() << 9621 (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); 9622 9623 DspinDhccpParam::dspin_set( 9624 flit, 9625 dest, 9626 DspinDhccpParam::CLACK_DEST); 9627 9628 DspinDhccpParam::dspin_set( 9629 flit, 9630 r_cleanup_nline.read(), 9631 DspinDhccpParam::CLACK_SET); 9632 9633 DspinDhccpParam::dspin_set( 9634 flit, 9635 r_cleanup_way_index.read(), 9636 DspinDhccpParam::CLACK_WAY); 9637 9638 DspinDhccpParam::dspin_set( 9639 flit, 9640 cleanup_ack_type, 9641 DspinDhccpParam::CLACK_TYPE); 9642 9643 p_dspin_clack.eop = true; 9644 p_dspin_clack.write = true; 9645 p_dspin_clack.data = flit; 9646 } 9647 else 9648 { 9649 p_dspin_clack.write = false; 9650 p_dspin_clack.eop = false; 9651 p_dspin_clack.data = 0; 9637 case CLEANUP_SEND_CLACK: 9638 { 9639 uint8_t cleanup_ack_type; 9640 if (r_cleanup_inst.read()) 9641 { 9642 cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; 9643 } 9644 else 9645 { 9646 cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; 9647 } 9648 9649 uint64_t flit = 0; 9650 uint64_t dest = r_cleanup_srcid.read() << 9651 (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); 9652 9653 DspinDhccpParam::dspin_set( 9654 flit, 9655 dest, 9656 DspinDhccpParam::CLACK_DEST); 9657 9658 DspinDhccpParam::dspin_set( 9659 flit, 9660 r_cleanup_nline.read(), 9661 DspinDhccpParam::CLACK_SET); 9662 9663 DspinDhccpParam::dspin_set( 9664 flit, 9665 r_cleanup_way_index.read(), 9666 DspinDhccpParam::CLACK_WAY); 9667 9668 DspinDhccpParam::dspin_set( 9669 flit, 9670 cleanup_ack_type, 9671 DspinDhccpParam::CLACK_TYPE); 9672 9673 p_dspin_clack.eop = true; 9674 p_dspin_clack.write = true; 9675 p_dspin_clack.data = flit; 9676 break; 9677 } 9678 ///////////////////////////////////// 9679 case CLEANUP_TEST_HEADER: 9680 { 9681 uint64_t flit = 0; 9682 9683 DspinDhccpParam::dspin_set(flit, 9684 r_cc_test_srcid.read(), 9685 DspinDhccpParam::TEST_CLACK_DEST); 9686 9687 DspinDhccpParam::dspin_set(flit, 9688 1ULL, 9689 DspinDhccpParam::TEST_CLACK_TEST); 9690 9691 // TODO: Send MemoryCache SRCID too ? 9692 9693 p_dspin_clack.write = true; 9694 p_dspin_clack.eop = false; 9695 p_dspin_clack.data = flit; 9696 break; 9697 } 9698 //////////////////////////////////// 9699 case CLEANUP_TEST_SIGNATURE: 9700 { 9701 uint64_t data = 9702 DspinDhccpParam::dspin_get( 9703 m_cc_receive_to_cc_test_fifo.read(), 9704 DspinDhccpParam::TEST_P2M_SIGNATURE); 9705 9706 uint64_t lsb = (uint64_t)data & ((1 << 7) - 1); 9707 uint64_t flit = 0; 9708 DspinDhccpParam::dspin_set(flit, 9709 data | (lsb << 32), 9710 DspinDhccpParam::TEST_CLACK_SIGNATURE); 9711 9712 p_dspin_clack.write = true; 9713 p_dspin_clack.eop = true; 9714 p_dspin_clack.data = flit; 9715 break; 9716 } 9717 //////////////////////////////////// 9718 default: 9719 p_dspin_clack.write = false; 9720 p_dspin_clack.eop = false; 9721 p_dspin_clack.data = 0; 9722 break; 9652 9723 } 9653 9724
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