- Timestamp:
- Sep 6, 2010, 1:57:15 PM (14 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r79 r88 350 350 sc_signal<bool> r_itlb_k_read_dcache; // used for instruction tlb miss, request in data cache 351 351 sc_signal<bool> r_itlb_acc_dcache_req; // used for itlb update access bit via dcache 352 sc_signal<bool> r_itlb_acc_redo_req; // used for itlb update access bit via dcache 352 353 sc_signal<bool> r_dcache_rsp_itlb_error; // used for data cache rsp error when itlb miss 353 354 sc_signal<data_t> r_dcache_rsp_itlb_miss; // used for dcache rsp data when itlb miss -
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r84 r88 447 447 r_itlb_k_read_dcache = false; 448 448 r_itlb_acc_dcache_req = false; 449 r_itlb_acc_redo_req = false; 449 450 r_dcache_rsp_itlb_error = false; 450 451 … … 1368 1369 r_icache_fsm = ICACHE_ERROR; 1369 1370 } 1371 else if ( r_itlb_acc_redo_req ) 1372 { 1373 r_itlb_acc_redo_req = false; 1374 r_icache_fsm = ICACHE_IDLE; 1375 } 1370 1376 else 1371 1377 { … … 1382 1388 r_icache_fsm = ICACHE_ERROR; 1383 1389 } 1390 else if ( r_itlb_acc_redo_req ) 1391 { 1392 r_itlb_acc_redo_req = false; 1393 r_icache_inval_tlb_rsp = false; 1394 r_icache_fsm = ICACHE_IDLE; 1395 } 1384 1396 else 1385 1397 { … … 1568 1580 r_icache_fsm = ICACHE_ERROR; 1569 1581 } 1582 else if ( r_itlb_acc_redo_req ) 1583 { 1584 r_itlb_acc_redo_req = false; 1585 r_icache_fsm = ICACHE_IDLE; 1586 } 1570 1587 else 1571 1588 { … … 1582 1599 r_icache_fsm = ICACHE_ERROR; 1583 1600 } 1601 else if ( r_itlb_acc_redo_req ) 1602 { 1603 r_itlb_acc_redo_req = false; 1604 r_icache_inval_tlb_rsp = false; 1605 r_icache_fsm = ICACHE_IDLE; 1606 } 1584 1607 else 1585 1608 { … … 2258 2281 if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) ) 2259 2282 { 2260 r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true); 2283 bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true); 2284 assert(set_hit && "D$ IDLE ITLB set hit error"); 2261 2285 } 2262 2286 } … … 2581 2605 dcache_hit_c = false; 2582 2606 } 2583 2584 2607 if ( r_mmu_mode.read() & DATA_TLB_MASK ) 2585 2608 { … … 2701 2724 else // get PTBA to calculate the physical address of PTE 2702 2725 { 2703 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2704 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2705 r_dcache_tlb_ptba_read = true; 2706 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 2726 data_t ptba; 2727 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 2728 { 2729 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2730 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 2731 (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 2732 r_dcache_tlb_ll_dirty_req = true; 2733 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2734 2735 } 2736 else 2737 { 2738 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2739 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2740 r_dcache_tlb_ptba_read = true; 2741 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 2742 } 2707 2743 } 2708 2744 } … … 2813 2849 { 2814 2850 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2815 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2816 r_dcache_tlb_ptba_read = true; 2817 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 2851 data_t ptba; 2852 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 2853 { 2854 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 2855 r_dcache_tlb_ll_dirty_req = true; 2856 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2857 } 2858 else 2859 { 2860 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2861 r_dcache_tlb_ptba_read = true; 2862 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 2863 } 2818 2864 } 2819 2865 } … … 2941 2987 { 2942 2988 r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK; 2943 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2944 r_dcache_tlb_ptba_read = true; 2945 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 2989 data_t ptba; 2990 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 2991 { 2992 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 2993 r_dcache_tlb_ll_dirty_req = true; 2994 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2995 } 2996 else 2997 { 2998 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2999 r_dcache_tlb_ptba_read = true; 3000 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 3001 } 2946 3002 } 2947 3003 } … … 3121 3177 r_dcache_inval_tlb_rsp = false; 3122 3178 r_dcache_fsm = DCACHE_IDLE; 3179 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 3123 3180 break; 3124 3181 } … … 3153 3210 if ( r_dcache_tlb_ptba_read ) 3154 3211 { 3212 paddr_t tlb_dpaddr; 3213 data_t data; 3155 3214 r_dcache_tlb_ptba_read = false; 3156 //write_hit = r_dcache.write(((paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)), r_dcache_pte_update); 3157 //assert(write_hit && "Write on miss ignores data"); 3158 r_dcache_tlb_ll_dirty_req = true; 3159 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3160 //m_cpt_dcache_data_write++; 3161 m_cost_data_tlb_update_dirty_frz++; 3215 if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read( (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3) ,&data)) 3216 { 3217 r_dcache_tlb_ll_dirty_req = true; 3218 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3219 //m_cpt_dcache_data_write++; 3220 m_cpt_data_tlb_update_dirty++; 3221 m_cost_data_tlb_update_dirty_frz++; 3222 } 3223 else 3224 { 3225 r_dcache_fsm = DCACHE_IDLE; 3226 } 3162 3227 } 3163 3228 else … … 3181 3246 r_dcache_pte_update = tlb_data | PTE_L_MASK; 3182 3247 r_dcache_tlb_ll_acc_req = true; 3183 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));3184 //assert(write_hit && "Write on miss ignores data");3185 3248 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3186 //m_cpt_dcache_data_write++;3187 3249 m_cpt_data_tlb_update_acc++; 3188 3250 m_cost_data_tlb_update_acc_frz++; … … 3200 3262 r_dcache_pte_update = tlb_data | PTE_R_MASK; 3201 3263 r_dcache_tlb_ll_acc_req = true; 3202 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));3203 //assert(write_hit && "Write on miss ignores data");3204 3264 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3205 //m_cpt_dcache_data_write++;3206 3265 m_cpt_data_tlb_update_acc++; 3207 3266 m_cost_data_tlb_update_acc_frz++; … … 3381 3440 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 3382 3441 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 3442 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 3383 3443 break; 3384 3444 } … … 3388 3448 r_dcache_fsm = DCACHE_IDLE; 3389 3449 r_dcache_inval_tlb_rsp = false; 3450 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 3390 3451 break; 3391 3452 } … … 3399 3460 r_dcache_fsm = DCACHE_IDLE; 3400 3461 r_dcache_inval_rsp = false; 3462 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 3401 3463 break; 3402 3464 } … … 3425 3487 r_dcache_inval_tlb_rsp = false; 3426 3488 r_dcache_fsm = DCACHE_IDLE; 3489 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 3427 3490 break; 3428 3491 } … … 3433 3496 data_t rsp_dtlb_miss = 0; 3434 3497 paddr_t victim_index = 0; 3435 //bool write_hit = false;3436 3498 size_t way = 0; 3437 3499 size_t set = 0; … … 3445 3507 r_dcache_fsm = DCACHE_IDLE; 3446 3508 r_dcache_inval_rsp = false; 3509 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 3447 3510 break; 3448 3511 } … … 3487 3550 r_dcache_bad_vaddr = dreq.addr; 3488 3551 r_dcache_fsm = DCACHE_ERROR; 3552 if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false; 3489 3553 } 3490 3554 else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD … … 3497 3561 if ( r_dcache_tlb_ptba_read ) 3498 3562 { 3563 paddr_t tlb_dpaddr; 3564 data_t data; 3499 3565 r_dcache_tlb_ptba_read = false; 3500 //write_hit = r_dcache.write(((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)),r_dcache_pte_update); 3501 //assert(write_hit && "Write on miss ignores data"); 3502 r_dcache_tlb_ll_dirty_req = true; 3503 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3504 //m_cpt_dcache_data_write++; 3505 m_cpt_data_tlb_update_dirty++; 3506 m_cost_data_tlb_update_dirty_frz++; 3566 if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3),&data)) 3567 { 3568 r_dcache_tlb_ll_dirty_req = true; 3569 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3570 //m_cpt_dcache_data_write++; 3571 m_cpt_data_tlb_update_dirty++; 3572 m_cost_data_tlb_update_dirty_frz++; 3573 } 3574 else 3575 { 3576 r_dcache_fsm = DCACHE_IDLE; 3577 } 3507 3578 } 3508 3579 else … … 3525 3596 r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK; 3526 3597 r_dcache_tlb_ll_acc_req = true; 3527 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));3528 //assert(write_hit && "Write on miss ignores data");3529 3598 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3530 //m_cpt_dcache_data_write++;3531 3599 m_cpt_data_tlb_update_acc++; 3532 3600 m_cost_data_tlb_update_acc_frz++; … … 3544 3612 r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK; 3545 3613 r_dcache_tlb_ll_acc_req = true; 3546 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));3547 //assert(write_hit && "Write on miss ignores data");3548 3614 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3549 //m_cpt_dcache_data_write++;3550 3615 m_cpt_data_tlb_update_acc++; 3551 3616 m_cost_data_tlb_update_acc_frz++; … … 3576 3641 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 3577 3642 } 3578 r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 3643 bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 3644 assert(set_hit && "TLB1_UPDT set hit error"); 3579 3645 r_dcache_fsm = DCACHE_IDLE; 3580 3646 } … … 3610 3676 data_t tlb_data = 0; 3611 3677 data_t tlb_data_ppn = 0; 3612 //bool write_hit = false;3613 3678 bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data); 3614 3679 … … 3657 3722 r_dcache_ppn_update = tlb_data_ppn; 3658 3723 r_dcache_tlb_ll_acc_req = true; 3659 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));3660 //assert(write_hit && "Write on miss ignores data");3661 3724 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3662 //m_cpt_dcache_data_write++;3663 3725 m_cpt_data_tlb_update_acc++; 3664 3726 m_cost_data_tlb_update_acc_frz++; … … 3678 3740 r_dcache_ppn_update = tlb_data_ppn; 3679 3741 r_dcache_tlb_ll_acc_req = true; 3680 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));3681 //assert(write_hit && "Write on miss ignores data");3682 3742 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3683 //m_cpt_dcache_data_write++;3684 3743 m_cpt_data_tlb_update_acc++; 3685 3744 m_cost_data_tlb_update_acc_frz++; … … 3991 4050 r_dcache_ppn_update = tlb_data_ppn; 3992 4051 r_dcache_tlb_ll_acc_req = true; 3993 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));3994 //assert(write_hit && "Write on miss ignores data");3995 4052 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3996 //m_cpt_dcache_data_write++;3997 4053 m_cpt_data_tlb_update_acc++; 3998 4054 m_cost_data_tlb_update_acc_frz++; … … 4012 4068 r_dcache_ppn_update = tlb_data_ppn; 4013 4069 r_dcache_tlb_ll_acc_req = true; 4014 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));4015 //assert(write_hit && "Write on miss ignores data");4016 4070 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 4017 //m_cpt_dcache_data_write++;4018 4071 m_cpt_data_tlb_update_acc++; 4019 4072 m_cost_data_tlb_update_acc_frz++; … … 4044 4097 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 4045 4098 } 4046 r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 4099 bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); 4100 assert(set_hit && "TLB2_UPDT set hit error"); 4047 4101 r_dcache_fsm = DCACHE_IDLE; 4048 4102 } … … 4143 4197 } 4144 4198 if (clean) break; 4199 set = 0; 4145 4200 } 4146 4201 … … 4511 4566 { 4512 4567 r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK; 4513 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 4514 r_dcache_tlb_ptba_read = true; 4515 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 4568 data_t ptba; 4569 if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba)) 4570 { 4571 r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 4572 r_dcache_tlb_ll_dirty_req = true; 4573 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 4574 4575 } 4576 else 4577 { 4578 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 4579 r_dcache_tlb_ptba_read = true; 4580 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 4581 } 4516 4582 } 4517 4583 } … … 4680 4746 r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf); 4681 4747 4682 r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true); 4748 bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true); 4749 assert(set_hit && "ITLB_UPDT set hit error"); 4683 4750 bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss); 4684 4751 m_cpt_ins_tlb_occup_cache++; … … 4771 4838 if ( r_dcache_inval_rsp ) 4772 4839 { 4840 r_itlb_acc_dcache_req = false; 4841 r_itlb_acc_redo_req = true; 4773 4842 r_dcache_inval_rsp = false; 4774 4843 r_dcache_fsm = DCACHE_IDLE; … … 6009 6078 6010 6079 6080
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