- Timestamp:
- Nov 17, 2014, 10:47:55 AM (10 years ago)
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- 1 edited
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branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r853 r888 322 322 r_dcache_vci_sc_req("r_dcache_vci_sc_req"), 323 323 r_dcache_vci_sc_data("r_dcache_vci_sc_data"), 324 r_dcache_vci_ miss_trdid("r_dcache_vci_miss_trdid"),324 r_dcache_vci_wdt_trdid("r_dcache_vci_wdt_trdid"), 325 325 326 326 r_dcache_xtn_way("r_dcache_xtn_way"), … … 332 332 r_dcache_miss_set("r_dcache_miss_set"), 333 333 r_dcache_miss_inval("r_dcache_miss_inval"), 334 r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"), 335 r_dcache_miss_wdt("r_dcache_miss_wdt"), 334 335 r_dcache_wdt_max("r_dcache_wdt_max"), 336 r_dcache_wdt("r_dcache_wdt"), 336 337 r_dcache_wdt_timeout("r_dcache_wdt_timeout"), 337 338 … … 817 818 818 819 // Reset watchdog timer threshold to max value 819 r_dcache_ miss_wdt_max= UINT32_MAX;820 r_dcache_wdt_max = UINT32_MAX; 820 821 r_dcache_wdt_timeout = 0; 821 822 … … 2535 2536 2536 2537 case XTN_WDT_MAX: 2537 m_drsp.rdata = r_dcache_ miss_wdt_max.read();2538 m_drsp.rdata = r_dcache_wdt_max.read(); 2538 2539 m_drsp.valid = true; 2539 2540 m_drsp.error = false; … … 2680 2681 2681 2682 case XTN_WDT_MAX: 2682 r_dcache_ miss_wdt_max = m_dreq.wdata;2683 r_dcache_wdt_max = m_dreq.wdata; 2683 2684 m_drsp.valid = true; 2684 2685 r_dcache_fsm = DCACHE_IDLE; … … 2802 2803 #endif 2803 2804 // request a VCI DMISS transaction 2804 r_dcache_vci_ miss_trdid = r_dcache_wdt_timeout.read();2805 r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read(); 2805 2806 2806 2807 r_dcache_vci_paddr = paddr; … … 2851 2852 r_dcache_vci_unc_req = true; 2852 2853 r_dcache_fsm = DCACHE_UNC_WAIT; 2854 2855 // reset to 0 the watchdog timer 2856 r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read(); 2857 r_dcache_wdt = 0; 2853 2858 #if DEBUG_DCACHE 2854 2859 if (m_debug_dcache_fsm) … … 2922 2927 r_dcache_vci_unc_req = true; 2923 2928 r_dcache_fsm = DCACHE_UNC_WAIT; 2929 2930 // reset to 0 the watchdog timer 2931 r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read(); 2932 r_dcache_wdt = 0; 2924 2933 } 2925 2934 else … … 3199 3208 else // we must load the missing cache line in dcache 3200 3209 { 3201 r_dcache_vci_ miss_trdid = r_dcache_wdt_timeout.read();3210 r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read(); 3202 3211 3203 3212 r_dcache_vci_miss_req = true; … … 3476 3485 else // we must load the missing cache line in dcache 3477 3486 { 3478 r_dcache_vci_ miss_trdid = r_dcache_wdt_timeout.read();3487 r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read(); 3479 3488 3480 3489 r_dcache_fsm = DCACHE_MISS_SELECT; … … 4168 4177 r_dcache_miss_set = set; 4169 4178 4170 // reset to 0 the misswatchdog timer4171 r_dcache_ miss_wdt = 0;4179 // reset to 0 the watchdog timer 4180 r_dcache_wdt = 0; 4172 4181 4173 4182 if (cleanup) … … 4297 4306 } 4298 4307 4299 // increment MISS watchdog timer for black-hole detection 4300 r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1; 4301 if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) { 4308 // increment watchdog timer for black-hole detection 4309 r_dcache_wdt = r_dcache_wdt.read() + 1; 4310 if (r_dcache_wdt.read() == r_dcache_wdt_max.read()) 4311 { 4302 4312 r_mmu_detr = MMU_READ_DATA_TIMEOUT; 4303 4313 r_mmu_dbvar = r_dcache_save_vaddr.read(); … … 4540 4550 } 4541 4551 4552 // increment watchdog timer for black-hole detection 4553 r_dcache_wdt = r_dcache_wdt.read() + 1; 4554 if (r_dcache_wdt.read() == r_dcache_wdt_max.read()) 4555 { 4556 r_mmu_detr = MMU_READ_DATA_TIMEOUT; 4557 r_mmu_dbvar = m_dreq.addr; 4558 m_drsp.valid = true; 4559 m_drsp.error = true; 4560 r_dcache_fsm = DCACHE_IDLE; 4561 4562 // debug: this counter is used to detect an early WDT timeout. 4563 // It is sent as the data uncacheable transactions TRDID. When a 4564 // response is treated by the RSP FSM, the RTRDID is compared to 4565 // this counter to determine if a timeout was triggered during the 4566 // transaction. 4567 r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1; 4568 4569 #if DEBUG_DCACHE 4570 if (m_debug_dcache_fsm) 4571 { 4572 std::cout << " <PROC " << name() << " DCACHE_MISS_WAIT>" 4573 " watchdog timer exception" << std::endl; 4574 } 4575 #endif 4576 break; 4577 } 4578 4542 4579 if (r_vci_rsp_data_error.read()) // bus error 4543 4580 { … … 5397 5434 if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC) 5398 5435 { 5436 // debug: verify that the available response concerns the current transaction. 5437 assert(r_dcache_wdt_timeout.read() == p_vci.rtrdid.read()); 5438 5399 5439 r_vci_rsp_fsm = RSP_DATA_UNC; 5400 5440 } … … 6101 6141 p_vci.wdata = 0; 6102 6142 p_vci.be = 0xF; 6103 p_vci.trdid = r_dcache_vci_ miss_trdid.read();6143 p_vci.trdid = r_dcache_vci_wdt_trdid.read(); 6104 6144 p_vci.pktid = TYPE_READ_DATA_MISS; 6105 6145 p_vci.plen = m_dcache_words << 2; … … 6111 6151 p_vci.cmdval = true; 6112 6152 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; 6113 p_vci.wdata = 0;6153 p_vci.wdata = r_dcache_vci_wdt_trdid.read(); 6114 6154 p_vci.be = r_dcache_vci_unc_be.read(); 6115 6155 p_vci.trdid = 0; … … 6125 6165 p_vci.wdata = r_dcache_vci_wdata.read(); 6126 6166 p_vci.be = r_dcache_vci_unc_be.read(); 6127 p_vci.trdid = 0;6167 p_vci.trdid = r_dcache_vci_wdt_trdid.read(); 6128 6168 p_vci.pktid = TYPE_DATA_UNC; 6129 6169 p_vci.plen = 4;
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