Index: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 853)
+++ branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 888)
@@ -442,5 +442,5 @@
     sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
     sc_signal<uint32_t>     r_dcache_vci_sc_data;       // SC data (command)
-    sc_signal<trdid_t>      r_dcache_vci_miss_trdid;    // miss dcache trdid (for debug)
+    sc_signal<trdid_t>      r_dcache_vci_wdt_trdid;     // dcache WDT trdid (for debug)
 
     // register used for XTN inval
@@ -456,7 +456,7 @@
     sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
 
-    // Watchdog timer (WDT) for MISS timeout exception (black-hole detection)
-    sc_signal<uint32_t>     r_dcache_miss_wdt_max;      // wdt triggering value
-    sc_signal<uint32_t>     r_dcache_miss_wdt;          // wdt counter
+    // Watchdog timer (WDT) for timeout exception (black-hole detection)
+    sc_signal<uint32_t>     r_dcache_wdt_max;           // wdt triggering value
+    sc_signal<uint32_t>     r_dcache_wdt;               // wdt counter
     sc_signal<trdid_t>      r_dcache_wdt_timeout;       // timeout counter (for debug)
 
Index: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 853)
+++ branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 888)
@@ -322,5 +322,5 @@
       r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
       r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
-      r_dcache_vci_miss_trdid("r_dcache_vci_miss_trdid"),
+      r_dcache_vci_wdt_trdid("r_dcache_vci_wdt_trdid"),
 
       r_dcache_xtn_way("r_dcache_xtn_way"),
@@ -332,6 +332,7 @@
       r_dcache_miss_set("r_dcache_miss_set"),
       r_dcache_miss_inval("r_dcache_miss_inval"),
-      r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"),
-      r_dcache_miss_wdt("r_dcache_miss_wdt"),
+
+      r_dcache_wdt_max("r_dcache_wdt_max"),
+      r_dcache_wdt("r_dcache_wdt"),
       r_dcache_wdt_timeout("r_dcache_wdt_timeout"),
 
@@ -817,5 +818,5 @@
 
         // Reset watchdog timer threshold to max value
-        r_dcache_miss_wdt_max      = UINT32_MAX;
+        r_dcache_wdt_max           = UINT32_MAX;
         r_dcache_wdt_timeout       = 0;
 
@@ -2535,5 +2536,5 @@
 
                     case XTN_WDT_MAX:
-                        m_drsp.rdata = r_dcache_miss_wdt_max.read();
+                        m_drsp.rdata = r_dcache_wdt_max.read();
                         m_drsp.valid = true;
                         m_drsp.error = false;
@@ -2680,5 +2681,5 @@
 
                     case XTN_WDT_MAX:
-                        r_dcache_miss_wdt_max = m_dreq.wdata;
+                        r_dcache_wdt_max = m_dreq.wdata;
                         m_drsp.valid = true;
                         r_dcache_fsm = DCACHE_IDLE;
@@ -2802,5 +2803,5 @@
 #endif
                                 // request a VCI DMISS transaction
-                                r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
+                                r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
 
                                 r_dcache_vci_paddr    = paddr;
@@ -2851,4 +2852,8 @@
                             r_dcache_vci_unc_req   = true;
                             r_dcache_fsm           = DCACHE_UNC_WAIT;
+
+                            // reset to 0 the watchdog timer
+                            r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
+                            r_dcache_wdt = 0;
 #if DEBUG_DCACHE
                             if (m_debug_dcache_fsm)
@@ -2922,4 +2927,8 @@
                                 r_dcache_vci_unc_req   = true;
                                 r_dcache_fsm           = DCACHE_UNC_WAIT;
+
+                                // reset to 0 the watchdog timer
+                                r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
+                                r_dcache_wdt = 0;
                             }
                             else
@@ -3199,5 +3208,5 @@
         else // we must load the missing cache line in dcache
         {
-            r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
+            r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
 
             r_dcache_vci_miss_req = true;
@@ -3476,5 +3485,5 @@
         else            // we must load the missing cache line in dcache
         {
-            r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read();
+            r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
 
             r_dcache_fsm          = DCACHE_MISS_SELECT;
@@ -4168,6 +4177,6 @@
             r_dcache_miss_set = set;
 
-            // reset to 0 the miss watchdog timer
-            r_dcache_miss_wdt = 0;
+            // reset to 0 the watchdog timer
+            r_dcache_wdt = 0;
 
             if (cleanup)
@@ -4297,7 +4306,8 @@
         }
 
-        // increment MISS watchdog timer for black-hole detection
-        r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1;
-        if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) {
+        // increment watchdog timer for black-hole detection
+        r_dcache_wdt = r_dcache_wdt.read() + 1;
+        if (r_dcache_wdt.read() == r_dcache_wdt_max.read())
+        {
             r_mmu_detr   = MMU_READ_DATA_TIMEOUT;
             r_mmu_dbvar  = r_dcache_save_vaddr.read();
@@ -4540,4 +4550,31 @@
         }
 
+        // increment watchdog timer for black-hole detection
+        r_dcache_wdt = r_dcache_wdt.read() + 1;
+        if (r_dcache_wdt.read() == r_dcache_wdt_max.read())
+        {
+            r_mmu_detr   = MMU_READ_DATA_TIMEOUT;
+            r_mmu_dbvar  = m_dreq.addr;
+            m_drsp.valid = true;
+            m_drsp.error = true;
+            r_dcache_fsm = DCACHE_IDLE;
+
+            // debug: this counter is used to detect an early WDT timeout.
+            // It is sent as the data uncacheable transactions TRDID. When a
+            // response is treated by the RSP FSM, the RTRDID is compared to
+            // this counter to determine if a timeout was triggered during the
+            // transaction.
+            r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
+
+#if DEBUG_DCACHE
+            if (m_debug_dcache_fsm)
+            {
+                std::cout << "  <PROC " << name() << " DCACHE_MISS_WAIT>"
+                             "  watchdog timer exception" << std::endl;
+            }
+#endif
+            break;
+        }
+
         if (r_vci_rsp_data_error.read()) // bus error
         {
@@ -5397,4 +5434,7 @@
             if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
             {
+                // debug: verify that the available response concerns the current transaction.
+                assert(r_dcache_wdt_timeout.read() == p_vci.rtrdid.read());
+
                 r_vci_rsp_fsm = RSP_DATA_UNC;
             }
@@ -6101,5 +6141,5 @@
         p_vci.wdata   = 0;
         p_vci.be      = 0xF;
-        p_vci.trdid   = r_dcache_vci_miss_trdid.read();
+        p_vci.trdid   = r_dcache_vci_wdt_trdid.read();
         p_vci.pktid   = TYPE_READ_DATA_MISS;
         p_vci.plen    = m_dcache_words << 2;
@@ -6111,5 +6151,5 @@
         p_vci.cmdval  = true;
         p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
-        p_vci.wdata   = 0;
+        p_vci.wdata   = r_dcache_vci_wdt_trdid.read();
         p_vci.be      = r_dcache_vci_unc_be.read();
         p_vci.trdid   = 0;
@@ -6125,5 +6165,5 @@
         p_vci.wdata   = r_dcache_vci_wdata.read();
         p_vci.be      = r_dcache_vci_unc_be.read();
-        p_vci.trdid   = 0;
+        p_vci.trdid   = r_dcache_vci_wdt_trdid.read();
         p_vci.pktid   = TYPE_DATA_UNC;
         p_vci.plen    = 4;
