Changeset 891 for trunk/modules/vci_mem_cache/caba
- Timestamp:
- Nov 27, 2014, 7:37:58 PM (10 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r836 r891 1243 1243 // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors, 1244 1244 // and dispatch these commands to the proper FSM through dedicated FIFOs. 1245 // These READ/WRITE commands can be for the XRAM segment, or for the 1246 // CONFIG segment: 1245 1247 // 1246 // There are 5 types of commands accepted inthe XRAM segment:1248 // There are 5 types of commands accepted for the XRAM segment: 1247 1249 // - READ : A READ request has a length of 1 VCI flit. It can be a single word 1248 1250 // or an entire cache line, depending on the PLEN value => READ FSM … … 1254 1256 // acces key, second flit the data to write => WRITE FSM. 1255 1257 // 1256 // The READ/WRITE commands accepted in the configurationsegment are targeting1258 // The READ/WRITE commands accepted for the CONFIG segment are targeting 1257 1259 // configuration or status registers. They must contain one single flit. 1258 1260 // - For almost all addressable registers, the response is returned immediately. … … 1268 1270 { 1269 1271 #if DEBUG_MEMC_TGT_CMD 1270 if (m_debug) 1271 { 1272 std::cout << " <MEMC " << name() 1273 << " TGT_CMD_IDLE> Receive command from srcid " 1274 << std::hex << p_vci_tgt.srcid.read() 1275 << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; 1276 } 1272 if (m_debug) 1273 std::cout << " <MEMC " << name() 1274 << " TGT_CMD_IDLE> Receive command from srcid " 1275 << std::hex << p_vci_tgt.srcid.read() 1276 << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; 1277 1277 #endif 1278 1278 // checking segmentation violation … … 1307 1307 // ==> mask = 0b0100 = 0x4 1308 1308 assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) and 1309 1309 "The type specified in the pktid field is incompatible with the READ CMD"); 1310 1310 r_tgt_cmd_fsm = TGT_CMD_READ; 1311 1311 } … … 1315 1315 // ==> TYPE_WRITE = X100 with the TSAR encoding 1316 1316 // ==> mask = 0b0111 = 0x7 1317 assert((((p_vci_tgt.pktid.read() & 0x7) == 0x4) or ((p_vci_tgt.pktid.read() & 0x7) == 0x0)) and 1318 "The type specified in the pktid field is incompatible with the WRITE CMD"); 1317 assert((((p_vci_tgt.pktid.read() & 0x7) == 0x4) or 1318 ((p_vci_tgt.pktid.read() & 0x7) == 0x0)) and 1319 "The type specified in the pktid field is incompatible with the WRITE CMD"); 1319 1320 r_tgt_cmd_fsm = TGT_CMD_WRITE; 1320 1321 } … … 1325 1326 // ==> mask = 0b0111 = 0x7 1326 1327 assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) and 1327 1328 "The type specified in the pktid field is incompatible with the LL CMD"); 1328 1329 r_tgt_cmd_fsm = TGT_CMD_READ; 1329 1330 } … … 1337 1338 // ==> mask = 0b0101 = 0x5 1338 1339 assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) and 1339 1340 "The type specified in the pktid field is incompatible with the NOP CMD"); 1340 1341 1341 1342 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) … … 1356 1357 break; 1357 1358 1358 1359 /////////////////// 1359 1360 case TGT_CMD_ERROR: // response error must be sent 1360 1361 … … 1373 1374 1374 1375 #if DEBUG_MEMC_TGT_CMD 1375 if (m_debug) 1376 { 1377 std::cout << " <MEMC " << name() 1378 << " TGT_CMD_ERROR> Segmentation violation:" 1379 << " address = " << std::hex << p_vci_tgt.address.read() 1380 << " / srcid = " << p_vci_tgt.srcid.read() 1381 << " / trdid = " << p_vci_tgt.trdid.read() 1382 << " / pktid = " << p_vci_tgt.pktid.read() 1383 << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1384 } 1385 #endif 1386 } 1387 break; 1388 1389 //////////////////// 1376 if (m_debug) 1377 std::cout << " <MEMC " << name() 1378 << " TGT_CMD_ERROR> Segmentation violation:" 1379 << " address = " << std::hex << p_vci_tgt.address.read() 1380 << " / srcid = " << p_vci_tgt.srcid.read() 1381 << " / trdid = " << p_vci_tgt.trdid.read() 1382 << " / pktid = " << p_vci_tgt.pktid.read() 1383 << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; 1384 #endif 1385 } 1386 break; 1387 1388 //////////////////// 1390 1389 case TGT_CMD_CONFIG: // execute config request and return response 1391 1390 { … … 1435 1434 1436 1435 addr_t addr_lsb = p_vci_tgt.address.read() & m_config_addr_mask; 1437 1438 addr_t cell = (addr_lsb / vci_param_int::B); 1439 1440 size_t regr = cell & m_config_regr_idx_mask; 1441 1442 size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; 1436 addr_t cell = (addr_lsb / vci_param_int::B); 1437 size_t regr = cell & m_config_regr_idx_mask; 1438 size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; 1443 1439 1444 1440 bool need_rsp; … … 1471 1467 { 1472 1468 assert(((wdata % (m_words * vci_param_int::B)) == 0) and 1473 1469 "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); 1474 1470 1475 1471 need_rsp = true; … … 2063 2059 2064 2060 #if DEBUG_MEMC_CONFIG 2065 if (m_debug) 2066 { 2067 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 2068 << " / address = " << std::hex << r_config_address.read() 2069 << " / lines = " << std::dec << r_config_cmd_lines.read() 2070 << " / type = " << r_config_cmd.read() << std::endl; 2071 } 2061 if (m_debug) 2062 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 2063 << " / address = " << std::hex << r_config_address.read() 2064 << " / lines = " << std::dec << r_config_cmd_lines.read() 2065 << " / type = " << r_config_cmd.read() << std::endl; 2072 2066 #endif 2073 2067 } … … 2088 2082 2089 2083 #if DEBUG_MEMC_CONFIG 2090 if (m_debug) 2091 { 2092 std::cout << " <MEMC " << name() << " CONFIG_LOOP>" 2093 << " / address = " << std::hex << r_config_address.read() 2094 << " / lines not handled = " << std::dec << r_config_cmd_lines.read() 2095 << " / command = " << r_config_cmd.read() << std::endl; 2096 } 2084 if (m_debug) 2085 std::cout << " <MEMC " << name() << " CONFIG_LOOP>" 2086 << " / address = " << std::hex << r_config_address.read() 2087 << " / lines not handled = " << std::dec << r_config_cmd_lines.read() 2088 << " / command = " << r_config_cmd.read() << std::endl; 2097 2089 #endif 2098 2090 break; … … 2107 2099 2108 2100 #if DEBUG_MEMC_CONFIG 2109 if (m_debug) 2110 { 2111 std::cout << " <MEMC " << name() << " CONFIG_WAIT>" 2112 << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; 2113 } 2101 if (m_debug) 2102 std::cout << " <MEMC " << name() << " CONFIG_WAIT>" 2103 << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; 2114 2104 #endif 2115 2105 break; … … 2128 2118 2129 2119 #if DEBUG_MEMC_CONFIG 2130 if (m_debug) 2131 { 2132 std::cout << " <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to send response:" 2133 << " error = " << r_config_to_tgt_rsp_error.read() 2134 << " / rsrcid = " << std::hex << r_config_srcid.read() 2135 << " / rtrdid = " << std::hex << r_config_trdid.read() 2136 << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; 2137 } 2120 if (m_debug) 2121 std::cout << " <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to send response:" 2122 << " error = " << r_config_to_tgt_rsp_error.read() 2123 << " / rsrcid = " << std::hex << r_config_srcid.read() 2124 << " / rtrdid = " << std::hex << r_config_trdid.read() 2125 << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; 2138 2126 #endif 2139 2127 } … … 2149 2137 2150 2138 #if DEBUG_MEMC_CONFIG 2151 if (m_debug) 2152 { 2153 std::cout << " <MEMC " << name() << " CONFIG_DIR_REQ>" 2154 << " Request DIR access" << std::endl; 2155 } 2139 if (m_debug) 2140 std::cout << " <MEMC " << name() << " CONFIG_DIR_REQ>" 2141 << " Request DIR access" << std::endl; 2156 2142 #endif 2157 2143 break; … … 2193 2179 2194 2180 #if DEBUG_MEMC_CONFIG 2195 if (m_debug) 2196 { 2197 std::cout << " <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: " 2198 << " address = " << std::hex << r_config_address.read() 2199 << " / hit = " << std::dec << entry.valid 2200 << " / dirty = " << entry.dirty 2201 << " / count = " << entry.count 2202 << " / is_cnt = " << entry.is_cnt << std::endl; 2203 } 2181 if (m_debug) 2182 std::cout << " <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: " 2183 << " address = " << std::hex << r_config_address.read() 2184 << " / hit = " << std::dec << entry.valid 2185 << " / dirty = " << entry.dirty 2186 << " / count = " << entry.count 2187 << " / is_cnt = " << entry.is_cnt << std::endl; 2204 2188 #endif 2205 2189 break; … … 2248 2232 2249 2233 #if DEBUG_MEMC_CONFIG 2250 if (m_debug) 2251 { 2252 std::cout << " <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: " 2253 << " wok = " << std::dec << wok 2254 << " index = " << index << std::endl; 2255 } 2234 if (m_debug) 2235 std::cout << " <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: " 2236 << " wok = " << std::dec << wok 2237 << " index = " << index << std::endl; 2256 2238 #endif 2257 2239 } … … 2260 2242 //////////////////// 2261 2243 case CONFIG_TRT_SET: // read data in cache 2262 // and post a PUT request in TRT2244 // and post a PUT request in TRT 2263 2245 { 2264 2246 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and … … 2297 2279 2298 2280 #if DEBUG_MEMC_CONFIG 2299 if (m_debug) 2300 { 2301 std::cout << " <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:" 2302 << " address = " << std::hex << r_config_address.read() 2303 << " index = " << std::dec << r_config_trt_index.read() << std::endl; 2304 } 2281 if (m_debug) 2282 std::cout << " <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:" 2283 << " address = " << std::hex << r_config_address.read() 2284 << " index = " << std::dec << r_config_trt_index.read() << std::endl; 2305 2285 #endif 2306 2286 break; … … 2320 2300 2321 2301 #if DEBUG_MEMC_CONFIG 2322 if (m_debug) 2323 { 2324 std::cout << " <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM" 2325 << " / address = " << std::hex << r_config_address.read() << std::endl; 2326 } 2302 if (m_debug) 2303 std::cout << " <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM" 2304 << " / address = " << std::hex << r_config_address.read() << std::endl; 2327 2305 #endif 2328 2306 } … … 2352 2330 2353 2331 #if DEBUG_MEMC_CONFIG 2354 if (m_debug) 2355 { 2356 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 2357 << " No copies in L1 : inval DIR entry" << std::endl; 2358 } 2332 if (m_debug) 2333 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 2334 << " No copies in L1 : inval DIR entry" << std::endl; 2359 2335 #endif 2360 2336 } … … 2396 2372 2397 2373 #if DEBUG_MEMC_CONFIG 2398 if (m_debug) 2399 { 2400 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 2401 << " Inval DIR entry and register inval in IVT" 2402 << " / index = " << std::dec << index 2403 << " / broadcast = " << broadcast << std::endl; 2404 } 2374 if (m_debug) 2375 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 2376 << " Inval DIR entry and register inval in IVT" 2377 << " / index = " << std::dec << index 2378 << " / broadcast = " << broadcast << std::endl; 2405 2379 #endif 2406 2380 } … … 2410 2384 2411 2385 #if DEBUG_MEMC_CONFIG 2412 if (m_debug) 2413 { 2414 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 2415 << " IVT full : release DIR & IVT locks and retry" << std::endl; 2416 } 2386 if (m_debug) 2387 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 2388 << " IVT full : release DIR & IVT locks and retry" << std::endl; 2417 2389 #endif 2418 2390 } … … 2439 2411 2440 2412 #if DEBUG_MEMC_CONFIG 2441 if (m_debug) 2442 { 2443 std::cout << " <MEMC " << name() << " CONFIG_BC_SEND>" 2444 << " Post a broadcast inval request to CC_SEND FSM" 2445 << " / address = " << r_config_address.read() <<std::endl; 2446 } 2413 if (m_debug) 2414 std::cout << " <MEMC " << name() << " CONFIG_BC_SEND>" 2415 << " Post a broadcast inval request to CC_SEND FSM" 2416 << " / address = " << r_config_address.read() <<std::endl; 2447 2417 #endif 2448 2418 } … … 2454 2424 if (not r_config_to_cc_send_multi_req.read() and 2455 2425 not r_config_to_cc_send_brdcast_req.read()) 2426 { 2427 // post first copy into FIFO 2428 config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); 2429 config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); 2430 config_to_cc_send_fifo_put = true; 2431 2432 if (r_config_dir_count.read() == 1) // only one copy 2433 { 2434 // post multi inval request 2435 r_config_to_cc_send_multi_req = true; 2436 r_config_to_cc_send_brdcast_req = false; 2437 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 2438 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 2439 2440 // prepare next iteration (next line to be invalidated) 2441 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2442 r_config_address = r_config_address.read() + (m_words << 2); 2443 r_config_fsm = CONFIG_LOOP; 2444 } 2445 else // several copies : must use heap 2446 { 2447 r_config_fsm = CONFIG_HEAP_REQ; 2448 } 2449 2450 #if DEBUG_MEMC_CONFIG 2451 if (m_debug) 2452 std::cout << " <MEMC " << name() << " CONFIG_INVAL_SEND>" 2453 << " Post multi inval request to CC_SEND FSM" 2454 << " / address = " << std::hex << r_config_address.read() 2455 << " / copy = " << r_config_dir_copy_srcid.read() 2456 << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; 2457 #endif 2458 } 2459 break; 2460 } 2461 ///////////////////// 2462 case CONFIG_HEAP_REQ: // Try to get access to Heap 2463 { 2464 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) 2465 { 2466 r_config_fsm = CONFIG_HEAP_SCAN; 2467 r_config_heap_next = r_config_dir_ptr.read(); 2468 } 2469 2470 #if DEBUG_MEMC_CONFIG 2471 if (m_debug) 2472 std::cout << " <MEMC " << name() << " CONFIG_HEAP_REQ>" 2473 << " Requesting HEAP lock" << std::endl; 2474 #endif 2475 break; 2476 } 2477 ////////////////////// 2478 case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM 2479 { 2480 HeapEntry entry = m_heap.read(r_config_heap_next.read()); 2481 bool last_copy = (entry.next == r_config_heap_next.read()); 2482 2483 // post one more copy into fifo 2484 config_to_cc_send_fifo_srcid = entry.owner.srcid; 2485 config_to_cc_send_fifo_inst = entry.owner.inst; 2486 config_to_cc_send_fifo_put = true; 2487 2488 assert ( (m_config_to_cc_send_inst_fifo.wok()) and 2489 "MEMC ERROR in CONFIG_HEAP_SCAN: The m_config_to_cc_send fifo should never overflow"); 2490 2491 r_config_heap_next = entry.next; 2492 if (last_copy) 2456 2493 { 2457 2494 // post multi inval request … … 2461 2498 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 2462 2499 2463 // post data into FIFO 2464 config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); 2465 config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); 2466 config_to_cc_send_fifo_put = true; 2467 2468 if (r_config_dir_count.read() == 1) // one copy 2469 { 2470 // prepare next iteration 2471 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2472 r_config_address = r_config_address.read() + (m_words << 2); 2473 r_config_fsm = CONFIG_LOOP; 2474 } 2475 else // several copies 2476 { 2477 r_config_fsm = CONFIG_HEAP_REQ; 2478 } 2479 2500 // prepare next iteration (next line to be invalidated) 2501 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2502 r_config_address = r_config_address.read() + (m_words << 2); 2503 r_config_fsm = CONFIG_HEAP_LAST; 2504 } 2480 2505 #if DEBUG_MEMC_CONFIG 2481 if (m_debug) 2482 { 2483 std::cout << " <MEMC " << name() << " CONFIG_INVAL_SEND>" 2484 << " Post multi inval request to CC_SEND FSM" 2485 << " / address = " << std::hex << r_config_address.read() 2486 << " / copy = " << r_config_dir_copy_srcid.read() 2487 << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; 2488 } 2489 #endif 2490 } 2491 break; 2492 } 2493 ///////////////////// 2494 case CONFIG_HEAP_REQ: // Try to get access to Heap 2495 { 2496 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) 2497 { 2498 r_config_fsm = CONFIG_HEAP_SCAN; 2499 r_config_heap_next = r_config_dir_ptr.read(); 2500 } 2501 2502 #if DEBUG_MEMC_CONFIG 2503 if (m_debug) 2504 { 2505 std::cout << " <MEMC " << name() << " CONFIG_HEAP_REQ>" 2506 << " Requesting HEAP lock" << std::endl; 2507 } 2508 #endif 2509 break; 2510 } 2511 ////////////////////// 2512 case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM 2513 { 2514 HeapEntry entry = m_heap.read(r_config_heap_next.read()); 2515 bool last_copy = (entry.next == r_config_heap_next.read()); 2516 2517 config_to_cc_send_fifo_srcid = entry.owner.srcid; 2518 config_to_cc_send_fifo_inst = entry.owner.inst; 2519 config_to_cc_send_fifo_put = true; 2520 2521 if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted 2522 { 2523 r_config_heap_next = entry.next; 2524 if (last_copy) r_config_fsm = CONFIG_HEAP_LAST; 2525 } 2526 2527 #if DEBUG_MEMC_CONFIG 2528 if (m_debug) 2529 { 2530 std::cout << " <MEMC " << name() << " CONFIG_HEAP_SCAN>" 2531 << " Post multi inval request to CC_SEND FSM" 2532 << " / address = " << std::hex << r_config_address.read() 2533 << " / copy = " << entry.owner.srcid 2534 << " / inst = " << std::dec << entry.owner.inst << std::endl; 2535 } 2506 if (m_debug) 2507 std::cout << " <MEMC " << name() << " CONFIG_HEAP_SCAN>" 2508 << " Post multi inval request to CC_SEND FSM" 2509 << " / address = " << std::hex << r_config_address.read() 2510 << " / copy = " << entry.owner.srcid 2511 << " / inst = " << std::dec << entry.owner.inst << std::endl; 2536 2512 #endif 2537 2513 break; … … 2558 2534 m_heap.write(r_config_heap_next.read(), last_entry); 2559 2535 2560 // prepare next iteration2561 r_config_cmd_lines = r_config_cmd_lines.read() - 1;2562 r_config_address = r_config_address.read() + (m_words << 2);2563 2536 r_config_fsm = CONFIG_LOOP; 2564 2537 2565 2538 #if DEBUG_MEMC_CONFIG 2566 if (m_debug) 2567 { 2568 std::cout << " <MEMC " << name() << " CONFIG_HEAP_LAST>" 2569 << " Heap housekeeping" << std::endl; 2570 } 2539 if (m_debug) 2540 std::cout << " <MEMC " << name() << " CONFIG_HEAP_LAST>" 2541 << " Heap housekeeping" << std::endl; 2571 2542 #endif 2572 2543 break; … … 5309 5280 5310 5281 #if DEBUG_MEMC_CLEANUP 5311 if (m_debug) 5312 { 5313 std::cout << " <MEMC " << name() 5314 << " CLEANUP_IDLE> Cleanup request:" << std::hex 5315 << " owner_id = " << srcid 5316 << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; 5317 } 5282 if (m_debug) 5283 std::cout << " <MEMC " << name() 5284 << " CLEANUP_IDLE> Cleanup request:" << std::hex 5285 << " owner_id = " << srcid 5286 << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; 5318 5287 #endif 5319 5288 break; … … 5334 5303 5335 5304 #if DEBUG_MEMC_CLEANUP 5336 if (m_debug) 5337 { 5338 std::cout << " <MEMC " << name() 5339 << " CLEANUP_GET_NLINE> Cleanup request:" 5340 << " address = " << std::hex << nline * m_words * 4 << std::endl; 5341 } 5305 if (m_debug) 5306 std::cout << " <MEMC " << name() 5307 << " CLEANUP_GET_NLINE> Cleanup request:" 5308 << " address = " << std::hex << nline * m_words * 4 << std::endl; 5342 5309 #endif 5343 5310 break; … … 5351 5318 5352 5319 #if DEBUG_MEMC_CLEANUP 5353 if (m_debug) 5354 { 5355 std::cout << " <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl; 5356 } 5320 if (m_debug) 5321 std::cout << " <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl; 5357 5322 #endif 5358 5323 break; … … 5398 5363 5399 5364 #if DEBUG_MEMC_CLEANUP 5400 if (m_debug) 5401 { 5402 std::cout << " <MEMC " << name() 5403 << " CLEANUP_DIR_LOCK> Test directory status: " 5404 << std::hex << " address = " << cleanup_address 5405 << " / hit = " << entry.valid 5406 << " / dir_id = " << entry.owner.srcid 5407 << " / dir_ins = " << entry.owner.inst 5408 << " / search_id = " << r_cleanup_srcid.read() 5409 << " / search_ins = " << r_cleanup_inst.read() 5410 << " / count = " << entry.count 5411 << " / is_cnt = " << entry.is_cnt << std::endl; 5412 } 5365 if (m_debug) 5366 std::cout << " <MEMC " << name() 5367 << " CLEANUP_DIR_LOCK> Test directory status: " 5368 << std::hex << " address = " << cleanup_address 5369 << " / hit = " << entry.valid 5370 << " / dir_id = " << entry.owner.srcid 5371 << " / dir_ins = " << entry.owner.inst 5372 << " / search_id = " << r_cleanup_srcid.read() 5373 << " / search_ins = " << r_cleanup_inst.read() 5374 << " / count = " << entry.count 5375 << " / is_cnt = " << entry.is_cnt << std::endl; 5413 5376 #endif 5414 5377 break; … … 5446 5409 5447 5410 #if DEBUG_MEMC_CLEANUP 5448 if (m_debug) 5449 { 5450 std::cout << " <MEMC " << name() 5451 << " CLEANUP_DIR_WRITE> Update directory:" 5452 << std::hex << " address = " << r_cleanup_nline.read() * m_words * 4 5453 << " / dir_id = " << entry.owner.srcid 5454 << " / dir_ins = " << entry.owner.inst 5455 << " / count = " << entry.count 5456 << " / is_cnt = " << entry.is_cnt << std::endl; 5457 } 5411 if (m_debug) 5412 std::cout << " <MEMC " << name() 5413 << " CLEANUP_DIR_WRITE> Update directory:" 5414 << std::hex << " address = " << r_cleanup_nline.read() * m_words * 4 5415 << " / dir_id = " << entry.owner.srcid 5416 << " / dir_ins = " << entry.owner.inst 5417 << " / count = " << entry.count 5418 << " / is_cnt = " << entry.is_cnt << std::endl; 5458 5419 #endif 5459 5420 … … 5468 5429 5469 5430 #if DEBUG_MEMC_CLEANUP 5470 if (m_debug) 5471 { 5472 std::cout << " <MEMC " << name() 5473 << " CLEANUP_HEAP_REQ> HEAP lock acquired " << std::endl; 5474 } 5431 if (m_debug) 5432 std::cout << " <MEMC " << name() 5433 << " CLEANUP_HEAP_REQ> HEAP lock acquired " << std::endl; 5475 5434 #endif 5476 5435 break; … … 5478 5437 ////////////////////// 5479 5438 case CLEANUP_HEAP_LOCK: // two cases are handled in this state : 5480 // 1. the matching copy is directly in the directory5481 // 2. the matching copy is the first copy in the heap5439 // 1. the matching copy is directly in the directory 5440 // 2. the matching copy is the first copy in the heap 5482 5441 { 5483 5442 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and … … 5556 5515 5557 5516 #if DEBUG_MEMC_CLEANUP 5558 if (m_debug) 5559 { 5560 std::cout << " <MEMC " << name() 5561 << " CLEANUP_HEAP_LOCK> Checks matching:" 5562 << " address = " << r_cleanup_nline.read() * m_words * 4 5563 << " / dir_id = " << r_cleanup_copy.read() 5564 << " / dir_ins = " << r_cleanup_copy_inst.read() 5565 << " / heap_id = " << heap_entry.owner.srcid 5566 << " / heap_ins = " << heap_entry.owner.inst 5567 << " / search_id = " << r_cleanup_srcid.read() 5568 << " / search_ins = " << r_cleanup_inst.read() << std::endl; 5569 } 5517 if (m_debug) 5518 std::cout << " <MEMC " << name() 5519 << " CLEANUP_HEAP_LOCK> Checks matching:" 5520 << " address = " << r_cleanup_nline.read() * m_words * 4 5521 << " / dir_id = " << r_cleanup_copy.read() 5522 << " / dir_ins = " << r_cleanup_copy_inst.read() 5523 << " / heap_id = " << heap_entry.owner.srcid 5524 << " / heap_ins = " << heap_entry.owner.inst 5525 << " / search_id = " << r_cleanup_srcid.read() 5526 << " / search_ins = " << r_cleanup_inst.read() << std::endl; 5570 5527 #endif 5571 5528 break; … … 5573 5530 //////////////////////// 5574 5531 case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy 5575 // is in the heap, but not the first in linked list5532 // is in the heap, but not the first in linked list 5576 5533 { 5577 5534 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and … … 5606 5563 5607 5564 #if DEBUG_MEMC_CLEANUP 5608 if (m_debug) 5609 { 5610 if (not match_heap) 5611 { 5612 std::cout 5613 << " <MEMC " << name() 5614 << " CLEANUP_HEAP_SEARCH> Matching copy not found, search next:" 5615 << std::endl; 5616 } 5617 else 5618 { 5619 std::cout 5620 << " <MEMC " << name() 5621 << " CLEANUP_HEAP_SEARCH> Matching copy found:" 5622 << std::endl; 5623 } 5624 std::cout 5625 << " address = " << r_cleanup_nline.read() * m_words * 4 5626 << " / heap_id = " << heap_entry.owner.srcid 5627 << " / heap_ins = " << heap_entry.owner.inst 5628 << " / search_id = " << r_cleanup_srcid.read() 5629 << " / search_ins = " << r_cleanup_inst.read() 5630 << " / last = " << last 5631 << std::endl; 5632 } 5565 if (m_debug) 5566 { 5567 if (not match_heap) 5568 { 5569 std::cout << " <MEMC " << name() 5570 << " CLEANUP_HEAP_SEARCH> Matching copy not found, search next:" 5571 << std::endl; 5572 } 5573 else 5574 { 5575 std::cout << " <MEMC " << name() 5576 << " CLEANUP_HEAP_SEARCH> Matching copy found:" 5577 << std::endl; 5578 } 5579 std::cout << " address = " << r_cleanup_nline.read() * m_words * 4 5580 << " / heap_id = " << heap_entry.owner.srcid 5581 << " / heap_ins = " << heap_entry.owner.inst 5582 << " / search_id = " << r_cleanup_srcid.read() 5583 << " / search_ins = " << r_cleanup_inst.read() 5584 << " / last = " << last 5585 << std::endl; 5586 } 5633 5587 #endif 5634 5588 break; … … 5659 5613 5660 5614 #if DEBUG_MEMC_CLEANUP 5661 if (m_debug) 5662 { 5663 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_SEARCH>" 5664 << " Remove the copy in the linked list" << std::endl; 5665 } 5615 if (m_debug) 5616 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_SEARCH>" 5617 << " Remove the copy in the linked list" << std::endl; 5666 5618 #endif 5667 5619 break; … … 5694 5646 5695 5647 #if DEBUG_MEMC_CLEANUP 5696 if (m_debug) 5697 { 5698 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_FREE>" 5699 << " Update the list of free entries" << std::endl; 5700 } 5648 if (m_debug) 5649 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_FREE>" 5650 << " Update the list of free entries" << std::endl; 5701 5651 #endif 5702 5652 break; … … 5704 5654 ////////////////////// 5705 5655 case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending 5706 // invalidate transaction matching the cleanup5656 // invalidate transaction matching the cleanup 5707 5657 { 5708 5658 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; … … 5718 5668 5719 5669 #if DEBUG_MEMC_CLEANUP 5720 if (m_debug) 5721 { 5722 std::cout << " <MEMC " << name() << " CLEANUP_IVT_LOCK>" 5723 << " Unexpected cleanup with no corresponding IVT entry:" 5724 << " address = " << std::hex << (r_cleanup_nline.read() * 4 * m_words) << std::endl; 5725 } 5670 if (m_debug) 5671 std::cout << " <MEMC " << name() << " CLEANUP_IVT_LOCK>" 5672 << " Unexpected cleanup with no corresponding IVT entry:" 5673 << " address = " << std::hex << (r_cleanup_nline.read() * 4 * m_words) << std::endl; 5726 5674 #endif 5727 5675 } … … 5737 5685 5738 5686 #if DEBUG_MEMC_CLEANUP 5739 if (m_debug) 5740 { 5741 std::cout << " <MEMC " << name() << " CLEANUP_IVT_LOCK>" 5742 << " Cleanup matching pending invalidate transaction on IVT:" 5743 << " address = " << std::hex << (r_cleanup_nline.read() * m_words * 4) 5744 << " / ivt_entry = " << index << std::endl; 5745 } 5687 if (m_debug) 5688 std::cout << " <MEMC " << name() << " CLEANUP_IVT_LOCK>" 5689 << " Cleanup matching pending invalidate transaction on IVT:" 5690 << " address = " << std::hex << (r_cleanup_nline.read() * m_words * 4) 5691 << " / ivt_entry = " << index << std::endl; 5746 5692 #endif 5747 5693 } … … 5762 5708 5763 5709 #if DEBUG_MEMC_CLEANUP 5764 if (m_debug) 5765 { 5766 std::cout << " <MEMC " << name() << " CLEANUP_IVT_DECREMENT>" 5767 << " Decrement response counter in IVT:" 5768 << " IVT_index = " << r_cleanup_index.read() 5769 << " / rsp_count = " << count << std::endl; 5770 } 5710 if (m_debug) 5711 std::cout << " <MEMC " << name() << " CLEANUP_IVT_DECREMENT>" 5712 << " Decrement response counter in IVT:" 5713 << " IVT_index = " << r_cleanup_index.read() 5714 << " / rsp_count = " << count << std::endl; 5771 5715 #endif 5772 5716 break; … … 5774 5718 /////////////////////// 5775 5719 case CLEANUP_IVT_CLEAR: // Clear IVT entry 5776 // Acknowledge CONFIG FSM if required5720 // Acknowledge CONFIG FSM if required 5777 5721 { 5778 5722 assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and 5779 5723 "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation"); 5780 5724 5781 5725 m_ivt.clear(r_cleanup_index.read()); … … 5784 5728 { 5785 5729 assert((r_config_rsp_lines.read() > 0) and 5786 5730 "MEMC ERROR in CLEANUP_IVT_CLEAR state"); 5787 5731 5788 5732 config_rsp_lines_cleanup_decr = true; … … 5793 5737 5794 5738 #if DEBUG_MEMC_CLEANUP 5795 if (m_debug) 5796 { 5797 std::cout << " <MEMC " << name() 5798 << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" 5799 << " IVT_index = " << r_cleanup_index.read() << std::endl; 5800 } 5739 if (m_debug) 5740 std::cout << " <MEMC " << name() 5741 << " CLEANUP_IVT_CLEAR> Clear entry in IVT:" 5742 << " IVT_index = " << r_cleanup_index.read() << std::endl; 5801 5743 #endif 5802 5744 break; … … 5816 5758 5817 5759 #if DEBUG_MEMC_CLEANUP 5818 if (m_debug) 5819 { 5820 std::cout << " <MEMC " << name() << " CLEANUP_WRITE_RSP>" 5821 << " Send a response to a previous write request: " 5822 << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() 5823 << " / rtrdid = " << r_cleanup_write_trdid.read() 5824 << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; 5825 } 5760 if (m_debug) 5761 std::cout << " <MEMC " << name() << " CLEANUP_WRITE_RSP>" 5762 << " Send a response to a previous write request: " 5763 << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() 5764 << " / rtrdid = " << r_cleanup_write_trdid.read() 5765 << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; 5826 5766 #endif 5827 5767 break; … … 5836 5776 5837 5777 #if DEBUG_MEMC_CLEANUP 5838 if (m_debug) 5839 { 5840 std::cout << " <MEMC " << name() 5841 << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:" 5842 << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 5843 << " / way = " << std::dec << r_cleanup_way.read() 5844 << " / srcid = " << std::hex << r_cleanup_srcid.read() 5845 << std::endl; 5846 } 5778 if (m_debug) 5779 std::cout << " <MEMC " << name() 5780 << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:" 5781 << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 5782 << " / way = " << std::dec << r_cleanup_way.read() 5783 << " / srcid = " << std::hex << r_cleanup_srcid.read() 5784 << std::endl; 5847 5785 #endif 5848 5786 break;
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