Changeset 898 for trunk/modules/vci_block_device_tsar/caba/source
- Timestamp:
- Dec 2, 2014, 11:35:59 AM (10 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp
r895 r898 2 2 * 3 3 * SOCLIB_LGPL_HEADER_BEGIN 4 * 4 * 5 5 * This file is part of SoCLib, GNU LGPLv2.1. 6 * 6 * 7 7 * SoCLib is free software; you can redistribute it and/or modify it 8 8 * under the terms of the GNU Lesser General Public License as published 9 9 * by the Free Software Foundation; version 2.1 of the License. 10 * 10 * 11 11 * SoCLib is distributed in the hope that it will be useful, but 12 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 14 * Lesser General Public License for more details. 15 * 15 * 16 16 * You should have received a copy of the GNU Lesser General Public 17 17 * License along with SoCLib; if not, write to the Free Software 18 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 19 19 * 02110-1301 USA 20 * 20 * 21 21 * SOCLIB_LGPL_HEADER_END 22 22 * … … 45 45 tmpl(void)::transition() 46 46 { 47 if(p_resetn.read() == false) 47 if(p_resetn.read() == false) 48 48 { 49 49 r_initiator_fsm = M_IDLE; … … 52 52 r_go = false; 53 53 return; 54 } 54 } 55 55 56 56 ////////////////////////////////////////////////////////////////////////////// … … 63 63 case T_IDLE: 64 64 { 65 if ( p_vci_target.cmdval.read() ) 66 { 65 if ( p_vci_target.cmdval.read() ) 66 { 67 67 r_srcid = p_vci_target.srcid.read(); 68 68 r_trdid = p_vci_target.trdid.read(); … … 72 72 bool found = false; 73 73 std::list<soclib::common::Segment>::iterator seg; 74 for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 74 for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 75 75 { 76 76 if ( seg->contains(address) ) found = true; 77 77 } 78 79 bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); 80 uint32_t cell = (uint32_t)((address & 0x3F)>>2); 78 79 bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); 80 uint32_t cell = (uint32_t)((address & 0x3F)>>2); 81 bool pending = (r_initiator_fsm.read() != M_IDLE); 81 82 82 83 if ( !read && not found ) r_target_fsm = T_WRITE_ERROR; … … 84 85 else if( !read && not p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; 85 86 else if( read && not p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; 87 else if( !read && pending ) r_target_fsm = T_WRITE_ERROR; 86 88 else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; 87 89 else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; … … 100 102 101 103 // get write data value for both 32 bits and 64 bits data width 102 if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) 104 if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) 103 105 r_tdata = (uint32_t)(p_vci_target.wdata.read()>>32); 104 106 else … … 110 112 case T_WRITE_BUFFER: 111 113 { 112 if (p_vci_target.rspack.read() ) 113 { 114 if (r_initiator_fsm.read() == M_IDLE) 115 { 116 114 if (p_vci_target.rspack.read() ) 115 { 117 116 #if DEBUG_BDEV 118 117 std::cout << " <BDEV_TGT WRITE_BUFFER> value = " << r_tdata.read() << std::endl; 119 118 #endif 120 r_buf_address = (uint64_t)r_tdata.read(); 121 r_target_fsm = T_IDLE; 122 } 119 r_buf_address = (uint64_t)r_tdata.read(); 120 r_target_fsm = T_IDLE; 123 121 } 124 122 break; … … 127 125 case T_WRITE_BUFFER_EXT: 128 126 { 129 if (p_vci_target.rspack.read() ) 130 { 131 if (r_initiator_fsm.read() == M_IDLE) 132 { 133 127 if (p_vci_target.rspack.read() ) 128 { 134 129 #if DEBUG_BDEV 135 130 std::cout << " <BDEV_TGT WRITE_BUFFER_EXT> value = " << r_tdata.read() << std::endl; 136 131 #endif 137 r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32); 138 r_target_fsm = T_IDLE; 139 } 132 r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32); 133 r_target_fsm = T_IDLE; 140 134 } 141 135 break; … … 144 138 case T_WRITE_COUNT: 145 139 { 146 if (p_vci_target.rspack.read() ) 147 { 148 if (r_initiator_fsm.read() == M_IDLE) 149 { 150 140 if (p_vci_target.rspack.read() ) 141 { 151 142 #if DEBUG_BDEV 152 143 std::cout << " <BDEV_TGT WRITE_COUNT> value = " << r_tdata.read() << std::endl; 153 144 #endif 154 r_nblocks = (uint32_t)r_tdata.read(); 155 r_target_fsm = T_IDLE; 156 } 145 r_nblocks = (uint32_t)r_tdata.read(); 146 r_target_fsm = T_IDLE; 157 147 } 158 148 break; … … 161 151 case T_WRITE_LBA: 162 152 { 163 if (p_vci_target.rspack.read() ) 164 { 165 if (r_initiator_fsm.read() == M_IDLE) 166 { 167 153 if (p_vci_target.rspack.read() ) 154 { 168 155 #if DEBUG_BDEV 169 156 std::cout << " <BDEV_TGT WRITE_LBA> value = " << r_tdata.read() << std::endl; 170 157 #endif 171 r_lba = (uint32_t)r_tdata.read(); 172 r_target_fsm = T_IDLE; 173 } 158 r_lba = (uint32_t)r_tdata.read(); 159 r_target_fsm = T_IDLE; 174 160 } 175 161 break; … … 178 164 case T_WRITE_OP: 179 165 { 180 if ( p_vci_target.rspack.read() ) 166 if ( p_vci_target.rspack.read() ) 181 167 { 182 168 if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_READ) and … … 215 201 case T_WRITE_IRQEN: 216 202 { 217 if ( p_vci_target.rspack.read() ) 203 if ( p_vci_target.rspack.read() ) 218 204 { 219 205 … … 243 229 case T_READ_STATUS: 244 230 { 245 if ( p_vci_target.rspack.read() ) 231 if ( p_vci_target.rspack.read() ) 246 232 { 247 233 r_target_fsm = T_IDLE; … … 254 240 } 255 241 } // end switch target fsm 256 242 257 243 ////////////////////////////////////////////////////////////////////////////// 258 244 // The initiator FSM executes a loop, transfering one block per iteration. … … 262 248 // and the number of bursts is (m_bursts_per_block). 263 249 // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) 264 // and first and last burst are shorter, because all words in a burst 250 // and first and last burst are shorter, because all words in a burst 265 251 // must be contained in a single cache line. 266 252 // first burst => nwords = m_words_per_burst - offset … … 271 257 switch( r_initiator_fsm.read() ) { 272 258 //////////// 273 case M_IDLE: 274 { 275 if ( r_go.read() ) 259 case M_IDLE: // check buffer alignment to compute the number of bursts 260 { 261 if ( r_go.read() ) 276 262 { 277 263 r_index = 0; … … 285 271 286 272 // start tranfer 287 if ( r_read.read() ) 273 if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; 288 274 else r_initiator_fsm = M_WRITE_BURST; 289 275 } 290 276 break; 291 } 277 } 292 278 ////////////////// 293 279 case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles … … 297 283 r_latency_count = m_latency; 298 284 ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); 299 if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) 285 if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) 300 286 { 301 287 r_initiator_fsm = M_READ_ERROR; 302 288 } 303 else 289 else 304 290 { 305 291 r_burst_count = 0; … … 309 295 310 296 //////////////////////////////////////////////////////////////////////////////////////// 311 //std::cout << "***** Block content after read for lba " 297 //std::cout << "***** Block content after read for lba " 312 298 // << std::hex << r_lba.read() << " **************" << std::endl; 313 299 //for ( size_t line=0 ; line<16 ; line++ ) … … 331 317 ////////////////// 332 318 case M_READ_BURST: // Compute the number of words and the number of flits in the burst 333 // The number of flits can be smaller than the number of words 319 // The number of flits can be smaller than the number of words 334 320 // in case of 8 bytes flits... 335 321 { … … 353 339 } 354 340 //////////////// 355 case M_READ_CMD: 341 case M_READ_CMD: // Send a multi-flits VCI WRITE command 356 342 { 357 343 if ( p_vci_initiator.cmdack.read() ) … … 359 345 uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); 360 346 361 if ( vci_param::B == 4 ) // one word per flit 347 if ( vci_param::B == 4 ) // one word per flit 362 348 { 363 349 if ( nwords <= 1 ) // last flit … … 386 372 r_words_count = r_words_count.read() + 2; 387 373 } 388 374 389 375 // compute next word address and next local buffer index 390 376 if ( nwords == 1 ) … … 403 389 } 404 390 //////////////// 405 case M_READ_RSP: 391 case M_READ_RSP: // Wait a single flit VCI WRITE response 406 392 { 407 393 if ( p_vci_initiator.rspval.read() ) … … 409 395 bool aligned = (r_burst_offset.read() == 0); 410 396 411 if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) 397 if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) 412 398 { 413 399 r_initiator_fsm = M_READ_ERROR; 414 400 } 415 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 401 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 416 402 (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) 417 403 { 418 if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block 404 if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block 419 405 { 420 406 r_initiator_fsm = M_READ_SUCCESS; … … 465 451 } 466 452 ///////////////// 467 case M_WRITE_CMD: 468 { 469 453 case M_WRITE_CMD: // This is actually a single flit VCI READ command 454 { 455 if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; 470 456 break; 471 457 } 472 458 ///////////////// 473 case M_WRITE_RSP: 459 case M_WRITE_RSP: // This is actually a multi-words VCI READ response 474 460 { 475 461 if ( p_vci_initiator.rspval.read() ) … … 491 477 if ( p_vci_initiator.reop.read() ) // last flit of the burst 492 478 { 493 494 r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); 495 496 if( (p_vci_initiator.rerror.read()&0x1) != 0 ) 479 r_words_count = 0; 480 r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); 481 482 if( (p_vci_initiator.rerror.read()&0x1) != 0 ) 497 483 { 498 484 r_initiator_fsm = M_WRITE_ERROR; 499 485 } 500 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 486 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 501 487 (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst 502 488 { … … 511 497 else 512 498 { 513 499 r_words_count = r_words_count.read() + 1; 514 500 } 515 501 } … … 517 503 } 518 504 /////////////////// 519 case M_WRITE_BLOCK: 505 case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles 520 506 { 521 507 if ( r_latency_count == 0 ) … … 523 509 524 510 //////////////////////////////////////////////////////////////////////////////////////// 525 //std::cout << "***** Block content before write for lba " 511 //std::cout << "***** Block content before write for lba " 526 512 // << std::hex << r_lba.read() << " ***********" << std::endl; 527 513 //for ( size_t line=0 ; line<16 ; line++ ) … … 540 526 if( ::write(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) 541 527 { 542 r_initiator_fsm = M_WRITE_ERROR; 543 } 544 else if ( r_block_count.read() == r_nblocks.read() - 1 ) 545 { 546 r_initiator_fsm = M_WRITE_SUCCESS; 528 r_initiator_fsm = M_WRITE_ERROR; 529 } 530 else if ( r_block_count.read() == r_nblocks.read() - 1 ) 531 { 532 r_initiator_fsm = M_WRITE_SUCCESS; 547 533 } 548 534 else … … 553 539 r_initiator_fsm = M_WRITE_BURST; 554 540 } 555 } 541 } 556 542 else 557 543 { … … 573 559 tmpl(void)::genMoore() 574 560 { 575 // p_vci_target port 561 // p_vci_target port 576 562 p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); 577 563 p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read(); … … 591 577 else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; 592 578 else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; 593 else if(r_initiator_fsm == M_READ_ERROR) 594 else if(r_initiator_fsm == M_WRITE_ERROR) 595 else 579 else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; 580 else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; 581 else p_vci_target.rdata = BLOCK_DEVICE_BUSY; 596 582 p_vci_target.rerror = VCI_READ_OK; 597 583 break; … … 668 654 669 655 switch (r_initiator_fsm) { 670 case M_WRITE_CMD: 656 case M_WRITE_CMD: // It is actually a single flit VCI read command 671 657 p_vci_initiator.rspack = false; 672 658 p_vci_initiator.cmdval = true; 673 659 p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); 674 660 p_vci_initiator.cmd = vci_param::CMD_READ; 675 p_vci_initiator.pktid = TYPE_READ_DATA_UNC; 661 p_vci_initiator.pktid = TYPE_READ_DATA_UNC; 676 662 p_vci_initiator.wdata = 0; 677 663 p_vci_initiator.be = 0; … … 679 665 p_vci_initiator.eop = true; 680 666 break; 681 case M_READ_CMD: // It is actually a multi-words VCI WRITE command667 case M_READ_CMD: // It is actually a multi-words VCI WRITE command 682 668 p_vci_initiator.rspack = false; 683 669 p_vci_initiator.cmdval = true; 684 p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); 670 p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); 685 671 p_vci_initiator.cmd = vci_param::CMD_WRITE; 686 672 p_vci_initiator.pktid = TYPE_WRITE; 687 673 p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nwords.read()<<2); 688 if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) 674 if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) 689 675 { 690 676 p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + 691 (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); 677 (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); 692 678 p_vci_initiator.be = 0xFF; 693 679 p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); … … 713 699 // IRQ signal 714 700 if ( ((r_initiator_fsm == M_READ_SUCCESS) || 715 701 (r_initiator_fsm == M_WRITE_SUCCESS) || 716 702 (r_initiator_fsm == M_READ_ERROR) || 717 (r_initiator_fsm == M_WRITE_ERROR) ) && 718 r_irq_enable.read() ) 703 (r_initiator_fsm == M_WRITE_ERROR) ) && 704 r_irq_enable.read() ) 719 705 { 720 706 … … 723 709 std::cout << " <BDEV_INI send IRQ>" << std::endl; 724 710 #endif 725 726 } 727 else 711 p_irq = true; 712 } 713 else 728 714 { 729 715 p_irq = false; … … 732 718 733 719 ////////////////////////////////////////////////////////////////////////////// 734 tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name name, 720 tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name name, 735 721 const soclib::common::MappingTable &mt, 736 722 const soclib::common::IntTab &srcid, … … 742 728 743 729 : caba::BaseModule(name), 744 745 746 747 748 749 750 751 752 753 754 p_irq("p_irq") 730 m_seglist(mt.getSegmentList(tgtid)), 731 m_srcid(mt.indexForId(srcid)), 732 m_words_per_block(block_size/4), 733 m_words_per_burst(burst_size/4), 734 m_bursts_per_block(block_size/burst_size), 735 m_latency(latency), 736 p_clk("p_clk"), 737 p_resetn("p_resetn"), 738 p_vci_initiator("p_vci_initiator"), 739 p_vci_target("p_vci_target"), 740 p_irq("p_irq") 755 741 { 756 742 std::cout << " - Building VciBlockDeviceTsar " << name << std::endl; 757 743 758 744 SC_METHOD(transition); 759 745 dont_initialize(); 760 746 sensitive << p_clk.pos(); 761 747 762 748 SC_METHOD(genMoore); 763 749 dont_initialize(); 764 750 sensitive << p_clk.neg(); … … 766 752 size_t nbsegs = 0; 767 753 std::list<soclib::common::Segment>::iterator seg; 768 for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 754 for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 769 755 { 770 756 nbsegs++; 771 772 if ( (seg->baseAddress() & 0x0000003F) != 0 ) 773 774 std::cout << "Error in component VciBlockDeviceTsar : " << name 775 757 758 if ( (seg->baseAddress() & 0x0000003F) != 0 ) 759 { 760 std::cout << "Error in component VciBlockDeviceTsar : " << name 761 << "The base address of segment " << seg->name() 776 762 << " must be multiple of 64 bytes" << std::endl; 777 778 779 if ( seg->size() < 64 ) 780 781 std::cout << "Error in component VciBlockDeviceTsar : " << name 782 763 exit(1); 764 } 765 if ( seg->size() < 64 ) 766 { 767 std::cout << "Error in component VciBlockDeviceTsar : " << name 768 << "The size of segment " << seg->name() 783 769 << " cannot be smaller than 64 bytes" << std::endl; 784 785 770 exit(1); 771 } 786 772 std::cout << " => segment " << seg->name() 787 773 << " / base = " << std::hex << seg->baseAddress() 788 << " / size = " << seg->size() << std::endl; 774 << " / size = " << seg->size() << std::endl; 789 775 } 790 776 791 777 if( nbsegs == 0 ) 792 778 { 793 794 795 796 } 797 798 if( (block_size != 128) && 799 (block_size != 256) && 800 (block_size != 512) && 779 std::cout << "Error in component VciBlockDeviceTsar : " << name 780 << " No segment allocated" << std::endl; 781 exit(1); 782 } 783 784 if( (block_size != 128) && 785 (block_size != 256) && 786 (block_size != 512) && 801 787 (block_size != 1024) && 802 (block_size != 2048) && 788 (block_size != 2048) && 803 789 (block_size != 4096) ) 804 805 806 790 { 791 std::cout << "Error in component VciBlockDeviceTsar : " << name 792 << " The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" 807 793 << std::endl; 808 809 810 811 if( (burst_size != 8 ) && 812 (burst_size != 16) && 813 (burst_size != 32) && 814 815 816 std::cout << "Error in component VciBlockDeviceTsar : " << name 817 818 819 820 821 822 823 std::cout << "Error in component VciBlockDeviceTsar : " << name 824 825 826 827 828 829 if ( m_fd < 0 ) 830 831 std::cout << "Error in component VciBlockDeviceTsar : " << name 832 833 834 835 836 837 if ( m_device_size > ((uint64_t)1<<vci_param::N ) ) 838 839 std::cout << "Error in component VciBlockDeviceTsar" << name 840 841 842 843 844 845 794 exit(1); 795 } 796 797 if( (burst_size != 8 ) && 798 (burst_size != 16) && 799 (burst_size != 32) && 800 (burst_size != 64) ) 801 { 802 std::cout << "Error in component VciBlockDeviceTsar : " << name 803 << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; 804 exit(1); 805 } 806 807 if ( (vci_param::B != 4) and (vci_param::B != 8) ) 808 { 809 std::cout << "Error in component VciBlockDeviceTsar : " << name 810 << " The VCI data fields must have 32 bits or 64 bits" << std::endl; 811 exit(1); 812 } 813 814 m_fd = ::open(filename.c_str(), O_RDWR); 815 if ( m_fd < 0 ) 816 { 817 std::cout << "Error in component VciBlockDeviceTsar : " << name 818 << " Unable to open file " << filename << std::endl; 819 exit(1); 820 } 821 m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; 822 823 if ( m_device_size > ((uint64_t)1<<vci_param::N ) ) 824 { 825 std::cout << "Error in component VciBlockDeviceTsar" << name 826 << " The file " << filename 827 << " has more blocks than addressable with the VCI address" << std::endl; 828 exit(1); 829 } 830 831 r_local_buffer = new uint32_t[m_words_per_block]; 846 832 847 833 } // end constructor … … 858 844 tmpl(void)::print_trace() 859 845 { 860 const char* initiator_str[] = 861 { 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 const char* target_str[] = 879 { 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 << " : " << target_str[r_target_fsm.read()] 901 << " / " << initiator_str[r_initiator_fsm.read()] 846 const char* initiator_str[] = 847 { 848 "INI_IDLE", 849 850 "INI_READ_BLOCK", 851 "INI_READ_BURST", 852 "INI_READ_CMD", 853 "INI_READ_RSP", 854 "INI_READ_SUCCESS", 855 "INI_READ_ERROR", 856 857 "INI_WRITE_BURST", 858 "INI_WRITE_CMD", 859 "INI_WRITE_RSP", 860 "INI_WRITE_BLOCK", 861 "INI_WRITE_SUCCESS", 862 "INI_WRITE_ERROR", 863 }; 864 const char* target_str[] = 865 { 866 "TGT_IDLE", 867 "TGT_WRITE_BUFFER", 868 "TGT_READ_BUFFER", 869 "TGT_WRITE_BUFFER_EXT", 870 "TGT_READ_BUFFER_EXT", 871 "TGT_WRITE_COUNT", 872 "TGT_READ_COUNT", 873 "TGT_WRITE_LBA", 874 "TGT_READ_LBA", 875 "TGT_WRITE_OP", 876 "TGT_READ_STATUS", 877 "TGT_WRITE_IRQEN", 878 "TGT_READ_IRQEN", 879 "TGT_READ_SIZE", 880 "TGT_READ_BLOCK", 881 "TGT_READ_ERROR", 882 "TGT_WRITE_ERROR ", 883 }; 884 885 std::cout << "BDEV " << name() 886 << " : " << target_str[r_target_fsm.read()] 887 << " / " << initiator_str[r_initiator_fsm.read()] 902 888 << " / buf = " << std::hex << r_buf_address.read() 903 889 << " / lba = " << std::hex << r_lba.read() 904 << " / block_count = " << std::dec << r_block_count.read() 905 << " / burst_count = " << r_burst_count.read() 906 << " / word_count = " << r_words_count.read() <<std::endl; 890 << " / block_count = " << std::dec << r_block_count.read() 891 << " / burst_count = " << r_burst_count.read() 892 << " / word_count = " << r_words_count.read() <<std::endl; 907 893 } 908 894
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