Changeset 899
- Timestamp:
- Dec 3, 2014, 1:49:53 PM (10 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r871 r899 1269 1269 // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors, 1270 1270 // and dispatch these commands to the proper FSM through dedicated FIFOs. 1271 // These READ/WRITE commands can be for the XRAM segment, or for the 1272 // CONFIG segment: 1271 1273 // 1272 // There are 5 types of commands accepted inthe XRAM segment:1274 // There are 5 types of commands accepted for the XRAM segment: 1273 1275 // - READ : A READ request has a length of 1 VCI flit. It can be a single word 1274 1276 // or an entire cache line, depending on the PLEN value => READ FSM … … 1280 1282 // acces key, second flit the data to write => WRITE FSM. 1281 1283 // 1282 // The READ/WRITE commands accepted in the configurationsegment are targeting1284 // The READ/WRITE commands accepted for the CONFIG segment are targeting 1283 1285 // configuration or status registers. They must contain one single flit. 1284 1286 // - For almost all addressable registers, the response is returned immediately. … … 1382 1384 break; 1383 1385 1384 1386 /////////////////// 1385 1387 case TGT_CMD_ERROR: // response error must be sent 1386 1388 … … 1413 1415 break; 1414 1416 1415 1417 //////////////////// 1416 1418 case TGT_CMD_CONFIG: // execute config request and return response 1417 1419 { … … 1461 1463 1462 1464 addr_t addr_lsb = p_vci_tgt.address.read() & m_config_addr_mask; 1463 1464 addr_t cell = (addr_lsb / vci_param_int::B); 1465 1466 size_t regr = cell & m_config_regr_idx_mask; 1467 1468 size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; 1465 addr_t cell = (addr_lsb / vci_param_int::B); 1466 size_t regr = cell & m_config_regr_idx_mask; 1467 size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; 1469 1468 1470 1469 bool need_rsp; … … 2286 2285 //////////////////// 2287 2286 case CONFIG_TRT_SET: // read data in cache 2288 // and post a PUT request in TRT2287 // and post a PUT request in TRT 2289 2288 { 2290 2289 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and … … 2481 2480 not r_config_to_cc_send_brdcast_req.read()) 2482 2481 { 2482 // post first copy into FIFO 2483 config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); 2484 config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); 2485 config_to_cc_send_fifo_put = true; 2486 2487 if (r_config_dir_count.read() == 1) // only one copy 2488 { 2489 // post multi inval request 2490 r_config_to_cc_send_multi_req = true; 2491 r_config_to_cc_send_brdcast_req = false; 2492 r_config_to_cc_send_trdid = r_config_ivt_index.read(); 2493 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 2494 2495 // prepare next iteration (next line to be invalidated) 2496 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2497 r_config_address = r_config_address.read() + (m_words << 2); 2498 r_config_fsm = CONFIG_LOOP; 2499 } 2500 else // several copies : must use heap 2501 { 2502 r_config_fsm = CONFIG_HEAP_REQ; 2503 } 2504 2505 #if DEBUG_MEMC_CONFIG 2506 if (m_debug) 2507 { 2508 std::cout << " <MEMC " << name() << " CONFIG_INVAL_SEND>" 2509 << " Post multi inval request to CC_SEND FSM" 2510 << " / address = " << std::hex << r_config_address.read() 2511 << " / copy = " << r_config_dir_copy_srcid.read() 2512 << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; 2513 } 2514 #endif 2515 } 2516 break; 2517 } 2518 ///////////////////// 2519 case CONFIG_HEAP_REQ: // Try to get access to Heap 2520 { 2521 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) 2522 { 2523 r_config_fsm = CONFIG_HEAP_SCAN; 2524 r_config_heap_next = r_config_dir_ptr.read(); 2525 } 2526 2527 #if DEBUG_MEMC_CONFIG 2528 if (m_debug) 2529 { 2530 std::cout << " <MEMC " << name() << " CONFIG_HEAP_REQ>" 2531 << " Requesting HEAP lock" << std::endl; 2532 } 2533 #endif 2534 break; 2535 } 2536 ////////////////////// 2537 case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM 2538 { 2539 HeapEntry entry = m_heap.read(r_config_heap_next.read()); 2540 bool last_copy = (entry.next == r_config_heap_next.read()); 2541 2542 // post one more copy into fifo 2543 config_to_cc_send_fifo_srcid = entry.owner.srcid; 2544 config_to_cc_send_fifo_inst = entry.owner.inst; 2545 config_to_cc_send_fifo_put = true; 2546 2547 assert ( (m_config_to_cc_send_inst_fifo.wok()) and 2548 "MEMC ERROR in CONFIG_HEAP_SCAN: The m_config_to_cc_send fifo should never overflow"); 2549 2550 r_config_heap_next = entry.next; 2551 if (last_copy) 2552 { 2483 2553 // post multi inval request 2484 2554 r_config_to_cc_send_multi_req = true; … … 2487 2557 r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; 2488 2558 2489 // post data into FIFO 2490 config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); 2491 config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); 2492 config_to_cc_send_fifo_put = true; 2493 2494 if (r_config_dir_count.read() == 1) // one copy 2495 { 2496 // prepare next iteration 2497 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2498 r_config_address = r_config_address.read() + (m_words << 2); 2499 r_config_fsm = CONFIG_LOOP; 2500 } 2501 else // several copies 2502 { 2503 r_config_fsm = CONFIG_HEAP_REQ; 2504 } 2505 2506 #if DEBUG_MEMC_CONFIG 2507 if (m_debug) 2508 { 2509 std::cout << " <MEMC " << name() << " CONFIG_INVAL_SEND>" 2510 << " Post multi inval request to CC_SEND FSM" 2511 << " / address = " << std::hex << r_config_address.read() 2512 << " / copy = " << r_config_dir_copy_srcid.read() 2513 << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; 2514 } 2515 #endif 2516 } 2517 break; 2518 } 2519 ///////////////////// 2520 case CONFIG_HEAP_REQ: // Try to get access to Heap 2521 { 2522 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) 2523 { 2524 r_config_fsm = CONFIG_HEAP_SCAN; 2525 r_config_heap_next = r_config_dir_ptr.read(); 2526 } 2527 2528 #if DEBUG_MEMC_CONFIG 2529 if (m_debug) 2530 { 2531 std::cout << " <MEMC " << name() << " CONFIG_HEAP_REQ>" 2532 << " Requesting HEAP lock" << std::endl; 2533 } 2534 #endif 2535 break; 2536 } 2537 ////////////////////// 2538 case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM 2539 { 2540 HeapEntry entry = m_heap.read(r_config_heap_next.read()); 2541 bool last_copy = (entry.next == r_config_heap_next.read()); 2542 2543 config_to_cc_send_fifo_srcid = entry.owner.srcid; 2544 config_to_cc_send_fifo_inst = entry.owner.inst; 2545 config_to_cc_send_fifo_put = true; 2546 2547 if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted 2548 { 2549 r_config_heap_next = entry.next; 2550 if (last_copy) r_config_fsm = CONFIG_HEAP_LAST; 2551 } 2552 2559 // prepare next iteration (next line to be invalidated) 2560 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2561 r_config_address = r_config_address.read() + (m_words << 2); 2562 r_config_fsm = CONFIG_HEAP_LAST; 2563 } 2553 2564 #if DEBUG_MEMC_CONFIG 2554 2565 if (m_debug) … … 2584 2595 m_heap.write(r_config_heap_next.read(), last_entry); 2585 2596 2586 // prepare next iteration2587 r_config_cmd_lines = r_config_cmd_lines.read() - 1;2588 r_config_address = r_config_address.read() + (m_words << 2);2589 2597 r_config_fsm = CONFIG_LOOP; 2590 2598 … … 5525 5533 ////////////////////// 5526 5534 case CLEANUP_HEAP_LOCK: // two cases are handled in this state : 5527 // 1. the matching copy is directly in the directory5528 // 2. the matching copy is the first copy in the heap5535 // 1. the matching copy is directly in the directory 5536 // 2. the matching copy is the first copy in the heap 5529 5537 { 5530 5538 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and … … 5620 5628 //////////////////////// 5621 5629 case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy 5622 // is in the heap, but not the first in linked list5630 // is in the heap, but not the first in linked list 5623 5631 { 5624 5632 assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and … … 5751 5759 ////////////////////// 5752 5760 case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending 5753 // invalidate transaction matching the cleanup5761 // invalidate transaction matching the cleanup 5754 5762 { 5755 5763 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; … … 5821 5829 /////////////////////// 5822 5830 case CLEANUP_IVT_CLEAR: // Clear IVT entry 5823 // Acknowledge CONFIG FSM if required5831 // Acknowledge CONFIG FSM if required 5824 5832 { 5825 5833 assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
Note: See TracChangeset
for help on using the changeset viewer.
