Index: /branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 898) +++ /branches/reconfiguration/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 899) @@ -1269,6 +1269,8 @@ // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors, // and dispatch these commands to the proper FSM through dedicated FIFOs. + // These READ/WRITE commands can be for the XRAM segment, or for the + // CONFIG segment: // - // There are 5 types of commands accepted in the XRAM segment: + // There are 5 types of commands accepted for the XRAM segment: // - READ : A READ request has a length of 1 VCI flit. It can be a single word // or an entire cache line, depending on the PLEN value => READ FSM @@ -1280,5 +1282,5 @@ // acces key, second flit the data to write => WRITE FSM. // - // The READ/WRITE commands accepted in the configuration segment are targeting + // The READ/WRITE commands accepted for the CONFIG segment are targeting // configuration or status registers. They must contain one single flit. // - For almost all addressable registers, the response is returned immediately. @@ -1382,5 +1384,5 @@ break; - /////////////////// + /////////////////// case TGT_CMD_ERROR: // response error must be sent @@ -1413,5 +1415,5 @@ break; - //////////////////// + //////////////////// case TGT_CMD_CONFIG: // execute config request and return response { @@ -1461,10 +1463,7 @@ addr_t addr_lsb = p_vci_tgt.address.read() & m_config_addr_mask; - - addr_t cell = (addr_lsb / vci_param_int::B); - - size_t regr = cell & m_config_regr_idx_mask; - - size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; + addr_t cell = (addr_lsb / vci_param_int::B); + size_t regr = cell & m_config_regr_idx_mask; + size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; bool need_rsp; @@ -2286,5 +2285,5 @@ //////////////////// case CONFIG_TRT_SET: // read data in cache - // and post a PUT request in TRT + // and post a PUT request in TRT { assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and @@ -2481,4 +2480,75 @@ not r_config_to_cc_send_brdcast_req.read()) { + // post first copy into FIFO + config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); + config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); + config_to_cc_send_fifo_put = true; + + if (r_config_dir_count.read() == 1) // only one copy + { + // post multi inval request + r_config_to_cc_send_multi_req = true; + r_config_to_cc_send_brdcast_req = false; + r_config_to_cc_send_trdid = r_config_ivt_index.read(); + r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; + + // prepare next iteration (next line to be invalidated) + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_LOOP; + } + else // several copies : must use heap + { + r_config_fsm = CONFIG_HEAP_REQ; + } + +#if DEBUG_MEMC_CONFIG + if (m_debug) + { + std::cout << " " + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << r_config_dir_copy_srcid.read() + << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; + } +#endif + } + break; + } + ///////////////////// + case CONFIG_HEAP_REQ: // Try to get access to Heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) + { + r_config_fsm = CONFIG_HEAP_SCAN; + r_config_heap_next = r_config_dir_ptr.read(); + } + +#if DEBUG_MEMC_CONFIG + if (m_debug) + { + std::cout << " " + << " Requesting HEAP lock" << std::endl; + } +#endif + break; + } + ////////////////////// + case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM + { + HeapEntry entry = m_heap.read(r_config_heap_next.read()); + bool last_copy = (entry.next == r_config_heap_next.read()); + + // post one more copy into fifo + config_to_cc_send_fifo_srcid = entry.owner.srcid; + config_to_cc_send_fifo_inst = entry.owner.inst; + config_to_cc_send_fifo_put = true; + + assert ( (m_config_to_cc_send_inst_fifo.wok()) and + "MEMC ERROR in CONFIG_HEAP_SCAN: The m_config_to_cc_send fifo should never overflow"); + + r_config_heap_next = entry.next; + if (last_copy) + { // post multi inval request r_config_to_cc_send_multi_req = true; @@ -2487,68 +2557,9 @@ r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; - // post data into FIFO - config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read(); - config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read(); - config_to_cc_send_fifo_put = true; - - if (r_config_dir_count.read() == 1) // one copy - { - // prepare next iteration - r_config_cmd_lines = r_config_cmd_lines.read() - 1; - r_config_address = r_config_address.read() + (m_words << 2); - r_config_fsm = CONFIG_LOOP; - } - else // several copies - { - r_config_fsm = CONFIG_HEAP_REQ; - } - -#if DEBUG_MEMC_CONFIG - if (m_debug) - { - std::cout << " " - << " Post multi inval request to CC_SEND FSM" - << " / address = " << std::hex << r_config_address.read() - << " / copy = " << r_config_dir_copy_srcid.read() - << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; - } -#endif - } - break; - } - ///////////////////// - case CONFIG_HEAP_REQ: // Try to get access to Heap - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) - { - r_config_fsm = CONFIG_HEAP_SCAN; - r_config_heap_next = r_config_dir_ptr.read(); - } - -#if DEBUG_MEMC_CONFIG - if (m_debug) - { - std::cout << " " - << " Requesting HEAP lock" << std::endl; - } -#endif - break; - } - ////////////////////// - case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM - { - HeapEntry entry = m_heap.read(r_config_heap_next.read()); - bool last_copy = (entry.next == r_config_heap_next.read()); - - config_to_cc_send_fifo_srcid = entry.owner.srcid; - config_to_cc_send_fifo_inst = entry.owner.inst; - config_to_cc_send_fifo_put = true; - - if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted - { - r_config_heap_next = entry.next; - if (last_copy) r_config_fsm = CONFIG_HEAP_LAST; - } - + // prepare next iteration (next line to be invalidated) + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_HEAP_LAST; + } #if DEBUG_MEMC_CONFIG if (m_debug) @@ -2584,7 +2595,4 @@ m_heap.write(r_config_heap_next.read(), last_entry); - // prepare next iteration - r_config_cmd_lines = r_config_cmd_lines.read() - 1; - r_config_address = r_config_address.read() + (m_words << 2); r_config_fsm = CONFIG_LOOP; @@ -5525,6 +5533,6 @@ ////////////////////// case CLEANUP_HEAP_LOCK: // two cases are handled in this state : - // 1. the matching copy is directly in the directory - // 2. the matching copy is the first copy in the heap + // 1. the matching copy is directly in the directory + // 2. the matching copy is the first copy in the heap { assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and @@ -5620,5 +5628,5 @@ //////////////////////// case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy - // is in the heap, but not the first in linked list + // is in the heap, but not the first in linked list { assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and @@ -5751,5 +5759,5 @@ ////////////////////// case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending - // invalidate transaction matching the cleanup + // invalidate transaction matching the cleanup { if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; @@ -5821,5 +5829,5 @@ /////////////////////// case CLEANUP_IVT_CLEAR: // Clear IVT entry - // Acknowledge CONFIG FSM if required + // Acknowledge CONFIG FSM if required { assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and