Index: /branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- /branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 900)
+++ /branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 901)
@@ -1300,6 +1300,8 @@
// The TGT_CMD_FSM controls the incoming VCI command pakets from the processors,
// and dispatch these commands to the proper FSM through dedicated FIFOs.
+ // These READ/WRITE commands can be for the XRAM segment, or for the
+ // CONFIG segment:
//
- // There are 5 types of commands accepted in the XRAM segment:
+ // There are 5 types of commands accepted for the XRAM segment:
// - READ : A READ request has a length of 1 VCI flit. It can be a single word
// or an entire cache line, depending on the PLEN value => READ FSM
@@ -1311,5 +1313,5 @@
// acces key, second flit the data to write => WRITE FSM.
//
- // The READ/WRITE commands accepted in the configuration segment are targeting
+ // The READ/WRITE commands accepted for the CONFIG segment are targeting
// configuration or status registers. They must contain one single flit.
// - For almost all addressable registers, the response is returned immediately.
@@ -1370,6 +1372,7 @@
// ==> TYPE_WRITE = X100 with the TSAR encoding
// ==> mask = 0b0111 = 0x7
- assert((((p_vci_tgt.pktid.read() & 0x7) == 0x4) or ((p_vci_tgt.pktid.read() & 0x7) == 0x0)) and
- "The type specified in the pktid field is incompatible with the WRITE CMD");
+ assert((((p_vci_tgt.pktid.read() & 0x7) == 0x4) or
+ ((p_vci_tgt.pktid.read() & 0x7) == 0x0)) and
+ "The type specified in the pktid field is incompatible with the WRITE CMD");
r_tgt_cmd_fsm = TGT_CMD_WRITE;
}
@@ -1411,5 +1414,5 @@
break;
- ///////////////////
+ ///////////////////
case TGT_CMD_ERROR: // response error must be sent
@@ -1442,5 +1445,5 @@
break;
- ////////////////////
+ ////////////////////
case TGT_CMD_CONFIG: // execute config request and return response
{
@@ -1490,9 +1493,6 @@
addr_t addr_lsb = p_vci_tgt.address.read() & m_config_addr_mask;
-
addr_t cell = (addr_lsb / vci_param_int::B);
-
size_t regr = cell & m_config_regr_idx_mask;
-
size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask;
@@ -2311,6 +2311,6 @@
}
////////////////////
- case CONFIG_TRT_SET: // read data in cache
- // and post a PUT request in TRT
+ case CONFIG_TRT_SET: // read data in cache
+ // and post a PUT request in TRT
{
assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
@@ -2480,8 +2480,8 @@
{
// post bc inval request
- r_config_to_cc_send_multi_req = false;
+ r_config_to_cc_send_multi_req = false;
r_config_to_cc_send_brdcast_req = true;
- r_config_to_cc_send_trdid = r_config_ivt_index.read();
- r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())];
+ r_config_to_cc_send_trdid = r_config_ivt_index.read();
+ r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())];
// prepare next iteration
@@ -2507,23 +2507,23 @@
not r_config_to_cc_send_brdcast_req.read())
{
- // post multi inval request
- r_config_to_cc_send_multi_req = true;
- r_config_to_cc_send_brdcast_req = false;
- r_config_to_cc_send_trdid = r_config_ivt_index.read();
- r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())];
-
- // post data into FIFO
+ // post first copy into FIFO
config_to_cc_send_fifo_srcid = r_config_dir_copy_srcid.read();
config_to_cc_send_fifo_inst = r_config_dir_copy_inst.read();
config_to_cc_send_fifo_put = true;
- if (r_config_dir_count.read() == 1) // one copy
- {
- // prepare next iteration
+ if (r_config_dir_count.read() == 1) // only one copy
+ {
+ // post multi inval request
+ r_config_to_cc_send_multi_req = true;
+ r_config_to_cc_send_brdcast_req = false;
+ r_config_to_cc_send_trdid = r_config_ivt_index.read();
+ r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())];
+
+ // prepare next iteration (next line to be invalidated)
r_config_cmd_lines = r_config_cmd_lines.read() - 1;
- r_config_address = r_config_address.read() + (m_words << 2);
- r_config_fsm = CONFIG_LOOP;
- }
- else // several copies
+ r_config_address = r_config_address.read() + (m_words << 2);
+ r_config_fsm = CONFIG_LOOP;
+ }
+ else // several copies : must use heap
{
r_config_fsm = CONFIG_HEAP_REQ;
@@ -2567,18 +2567,29 @@
bool last_copy = (entry.next == r_config_heap_next.read());
+ // post one more copy into fifo
config_to_cc_send_fifo_srcid = entry.owner.srcid;
- config_to_cc_send_fifo_inst = entry.owner.inst;
- config_to_cc_send_fifo_put = true;
-
- if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted
- {
- r_config_heap_next = entry.next;
- if (last_copy) r_config_fsm = CONFIG_HEAP_LAST;
-
- //
- m_cpt_heap_slot_available++;
- //
- }
-
+ config_to_cc_send_fifo_inst = entry.owner.inst;
+ config_to_cc_send_fifo_put = true;
+
+ assert ( (m_config_to_cc_send_inst_fifo.wok()) and
+ "MEMC ERROR in CONFIG_HEAP_SCAN: The m_config_to_cc_send fifo should never overflow");
+
+ r_config_heap_next = entry.next;
+ if (last_copy)
+ {
+ // post multi inval request
+ r_config_to_cc_send_multi_req = true;
+ r_config_to_cc_send_brdcast_req = false;
+ r_config_to_cc_send_trdid = r_config_ivt_index.read();
+ r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())];
+
+ // prepare next iteration (next line to be invalidated)
+ r_config_cmd_lines = r_config_cmd_lines.read() - 1;
+ r_config_address = r_config_address.read() + (m_words << 2);
+ r_config_fsm = CONFIG_HEAP_LAST;
+ }
+ //
+ m_cpt_heap_slot_available++;
+ //
#if DEBUG_MEMC_CONFIG
if (m_debug)
@@ -2614,7 +2625,4 @@
m_heap.write(r_config_heap_next.read(), last_entry);
- // prepare next iteration
- r_config_cmd_lines = r_config_cmd_lines.read() - 1;
- r_config_address = r_config_address.read() + (m_words << 2);
r_config_fsm = CONFIG_LOOP;