Changeset 912


Ignore:
Timestamp:
Jan 2, 2015, 1:18:51 PM (10 years ago)
Author:
alain
Message:

The hard lock implemented as an addressable register in the configuration interface
of the vci_mem_cache has been removed, as it created a possible live-lock situation.
It should be replaced by an external software queuing lock in case of concurrent access.
This lock was only used by the INVAL and SYNC request for software L2/L3 cache coherence.
The tsar_boot preloader and the giet-vm mmc_driver have been accordingly updated.

Location:
trunk/modules/vci_mem_cache
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

    r908 r912  
    469469        r_alloc_heap_fsm("r_alloc_heap_fsm"),
    470470        r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt")
     471
    471472#if MONITOR_MEMCACHE_FSM == 1
    472473        ,
    … …  
    879880    }
    880881
    881     /////////////////////////////////////////
     882    //////////////////////////////////////////////////////////////
    882883    tmpl(void)::print_stats(bool activity_counters, bool stats)
    883     /////////////////////////////////////////
     884    /////////////////////////////////////////////////////////////
    884885    {
    885886        std::cout << "**********************************" << std::dec << std::endl;
    … …  
    10581059
    10591060            r_config_cmd  = MEMC_CMD_NOP;
    1060             r_config_lock = false;
    10611061
    10621062            m_config_to_cc_send_inst_fifo.init();
    … …  
    14481448                    case MEMC_CONFIG:
    14491449                    {
    1450                         if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock
    1451                                 and (regr == MEMC_LOCK))
    1452                         {
    1453                             rdata         = (uint32_t) r_config_lock.read();
    1454                             need_rsp      = true;
    1455                             error         = 0;
    1456                             r_config_lock = true;
    1457                         }
    1458                         else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
    1459                                 and (regr == MEMC_LOCK))
    1460                         {
    1461                             need_rsp = true;
    1462                             error    = 0;
    1463                             r_config_lock = false;
    1464                         }
    1465                         else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
     1450                        if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
    14661451                                and (regr == MEMC_ADDR_LO))
    14671452                        {
    … …  
    19921977        //    CONFIG FSM
    19931978        ////////////////////////////////////////////////////////////////////////////////////
    1994         // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC).
     1979        // The CONFIG FSM handles the L2/L3 coherence requests:
    19951980        // The target buffer can have any size, and there is one single command for
    19961981        // all cache lines covered by the target buffer.
    1997         //
    1998         // An INVAL or SYNC configuration operation is defined by the following registers:
     1982        // An INVAL or SYNC operation is defined by the following registers:
    19991983        // - bool      r_config_cmd        : INVAL / SYNC / NOP
    20001984        // - uint64_t  r_config_address    : buffer base address
    … …  
    20362020        //   The CONFIG SYNC response is sent only when the last PUT response is received.
    20372021        //
    2038         // From the software point of view, a configuration request is a sequence
    2039         // of 6 atomic accesses in an uncached segment. A dedicated lock is used
    2040         // to handle only one configuration command at a given time:
    2041         // - Read  MEMC_LOCK       : Get the lock
     2022        // From the software point of view, a L2/L3 coherence request is a sequence
     2023        // of 4 atomic accesses in an uncached segment:
    20422024        // - Write MEMC_ADDR_LO    : Set the buffer address LSB
    20432025        // - Write MEMC_ADDR_HI    : Set the buffer address MSB
    20442026        // - Write MEMC_BUF_LENGTH : set buffer length (bytes)
    20452027        // - Write MEMC_CMD_TYPE   : launch the actual operation
    2046         // - WRITE MEMC_LOCK       : release the lock
    20472028        ////////////////////////////////////////////////////////////////////////////////////
    20482029

  • trunk/modules/vci_mem_cache/include/soclib/mem_cache.h

    r601 r912  
    3939enum SoclibMemCacheConfigRegs
    4040{
    41     MEMC_LOCK,
    4241    MEMC_ADDR_LO,
    4342    MEMC_ADDR_HI,
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