- Timestamp:
- Jan 9, 2015, 11:55:11 PM (10 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r903 r919 96 96 "DCACHE_XTN_DC_INVAL_GO", 97 97 "DCACHE_XTN_DT_INVAL", 98 "DCACHE_XTN_CC_TEST", 98 99 99 100 "DCACHE_DIRTY_GET_PTE", … … 172 173 "CC_RECEIVE_DATA_UPDT_NLINE", 173 174 "CC_RECEIVE_DATA_UPDT_DATA", 175 "CC_RECEIVE_TEST_HEADER", 176 "CC_RECEIVE_TEST_SIGNATURE", 174 177 }; 175 178 … … 179 182 "CC_SEND_CLEANUP_2", 180 183 "CC_SEND_MULTI_ACK", 184 "CC_SEND_TEST_HEADER", 185 "CC_SEND_TEST_SIGNATURE", 186 }; 187 188 const char * cc_test_fsm_state_str[] = { 189 "CC_TEST_IDLE", 190 "CC_TEST_P2M_REQ", 191 "CC_TEST_P2M_WAIT", 192 "CC_TEST_ACK_WAIT", 181 193 }; 182 194 } … … 371 383 r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"), 372 384 385 r_dcache_to_cc_test_req("r_dcache_to_cc_test_req"), 386 r_dcache_to_cc_test_dest("r_dcache_to_cc_test_dest"), 387 373 388 r_vci_cmd_fsm("r_vci_cmd_fsm"), 374 389 r_vci_cmd_min("r_vci_cmd_min"), … … 407 422 r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"), 408 423 r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"), 424 425 r_cc_test_fsm("r_cc_test_fsm"), 426 r_cc_test_to_cc_send_req("r_cc_test_to_cc_send_req"), 427 r_cc_test_m2p_req("r_cc_test_m2p_req"), 428 r_cc_test_m2p_sign("r_cc_test_m2p_sign"), 429 r_cc_test_clack_req("r_cc_test_clack_req"), 430 r_cc_test_clack_sign("r_cc_test_clack_sign"), 431 r_cc_test_to_dcache_result("r_cc_test_to_dcache_result"), 409 432 410 433 r_iss(this->name(), proc_id), … … 503 526 << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()] 504 527 << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] 528 << " | " << cc_test_fsm_state_str[r_cc_test_fsm.read()] 505 529 << " | MMU = " << r_mmu_mode.read(); 506 530 … … 762 786 r_cc_receive_fsm = CC_RECEIVE_IDLE; 763 787 r_cc_send_fsm = CC_SEND_IDLE; 788 r_cc_test_fsm = CC_TEST_IDLE; 764 789 765 790 // reset data physical address extension … … 837 862 838 863 r_dspin_clack_req = false; 864 r_dspin_clack_test = false; 865 866 r_cc_test_to_cc_send_req = false; 867 r_cc_test_m2p_req = false; 868 r_cc_test_clack_req = false; 839 869 840 870 // No signalisation of errors … … 2541 2571 break; 2542 2572 2573 case XTN_CC_TEST: 2574 m_drsp.rdata = r_cc_test_to_dcache_result.read(); 2575 m_drsp.valid = true; 2576 m_drsp.error = false; 2577 break; 2578 2543 2579 default: 2544 2580 r_mmu_detr = MMU_READ_UNDEFINED_XTN; … … 2684 2720 m_drsp.valid = true; 2685 2721 r_dcache_fsm = DCACHE_IDLE; 2722 break; 2723 2724 case XTN_CC_TEST: 2725 r_dcache_to_cc_test_dest = m_dreq.wdata; 2726 r_dcache_to_cc_test_req = true; 2727 r_dcache_fsm = DCACHE_XTN_CC_TEST; 2686 2728 break; 2687 2729 … … 4121 4163 r_dcache_fsm = DCACHE_IDLE; 4122 4164 m_drsp.valid = true; 4165 break; 4166 } 4167 ////////////////////////////// 4168 case DCACHE_XTN_CC_TEST: // wait the CC_TEST to finish 4169 { 4170 // coherence clack request (from DSPIN CLACK) 4171 if (r_dcache_clack_req.read()) 4172 { 4173 r_dcache_fsm = DCACHE_CC_CHECK; 4174 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4175 break; 4176 } 4177 4178 // coherence request (from CC_RECEIVE FSM) 4179 if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) 4180 { 4181 r_dcache_fsm = DCACHE_CC_CHECK; 4182 r_dcache_fsm_cc_save = r_dcache_fsm.read(); 4183 break; 4184 } 4185 4186 // wait the CC_TEST request to finish 4187 // the test result is stored at the r_cc_test_to_dcache_result 4188 if (not r_dcache_to_cc_test_req.read()) 4189 { 4190 r_dcache_fsm = DCACHE_IDLE; 4191 m_drsp.valid = true; 4192 4193 #if DEBUG_DCACHE 4194 if (m_debug_dcache_fsm) 4195 { 4196 std::cout << " <PROC " << name() 4197 << " DCACHE_XTN_CC_TEST> CC_TEST finished:" 4198 << std::hex 4199 << " / DEST = " << r_dcache_to_cc_test_dest.read() 4200 << " / RESULt = " << r_cc_test_to_dcache_result.read() 4201 << std::dec << std::endl; 4202 } 4203 #endif 4204 } 4123 4205 break; 4124 4206 } … … 5681 5763 { 5682 5764 /////////////////////////////////////////////////////// 5765 // Handle CC_TEST request // 5766 /////////////////////////////////////////////////////// 5767 if (r_cc_test_to_cc_send_req.read()) 5768 { 5769 r_cc_send_fsm = CC_SEND_TEST_HEADER; 5770 break; 5771 } 5772 5773 /////////////////////////////////////////////////////// 5683 5774 // handling round robin between icache and dcache : // 5684 5775 // we first check for the last client and listen for // … … 5761 5852 break; 5762 5853 } 5854 /////////////////////////// 5855 case CC_SEND_TEST_HEADER: 5856 { 5857 // the r_cc_test_to_cc_send_req can be reset by the CC_TEST FSM 5858 // when there is a watchdog timeout 5859 if (not r_cc_test_to_cc_send_req.read()) 5860 { 5861 r_cc_send_fsm = CC_SEND_IDLE; 5862 break; 5863 } 5864 5865 if (not p_dspin_p2m.read.read()) break; 5866 r_cc_send_fsm = CC_SEND_TEST_SIGNATURE; 5867 break; 5868 } 5869 /////////////////////////// 5870 case CC_SEND_TEST_SIGNATURE: 5871 { 5872 // the r_cc_test_to_cc_send_req can be reset by the CC_TEST FSM 5873 // when there is a watchdog timeout 5874 if (not p_dspin_p2m.read.read() and r_cc_test_to_cc_send_req.read()) break; 5875 r_cc_test_to_cc_send_req = false; 5876 r_cc_send_fsm = CC_SEND_IDLE; 5877 break; 5878 } 5763 5879 } // end switch CC_SEND FSM 5764 5880 … … 5772 5888 // - CC_INST_UPDT : ICACHE update request (multi-words) 5773 5889 // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) 5890 // - CC_TEST_M2P : M2P coherence network test packet 5774 5891 ////////////////////////////////////////////////////////////////////////////// 5775 5892 switch (r_cc_receive_fsm.read()) … … 5783 5900 // initialize dspin received data 5784 5901 uint64_t receive_data = p_dspin_m2p.data.read(); 5902 5903 // coherence test packet (CC_TEST_M2P) 5904 if (DspinDhccpParam::dspin_get(receive_data, DspinDhccpParam::TEST_M2P_TEST)) 5905 { 5906 r_cc_receive_fsm = CC_RECEIVE_TEST_HEADER; 5907 break; 5908 } 5909 5785 5910 // initialize coherence packet type 5786 5911 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, … … 5825 5950 uint64_t receive_data = p_dspin_m2p.data.read(); 5826 5951 // wait for both dcache and icache to take the request 5827 // TODO maybe we need to wait for both only to leave the state, but5828 // not to actually post a request to an available cache => need a5829 // flip_flop to check that ?5830 5952 if (not (r_cc_receive_icache_req.read()) and 5831 5953 not (r_cc_receive_dcache_req.read()) and … … 6004 6126 break; 6005 6127 } 6128 ////////////////////////// 6129 case CC_RECEIVE_TEST_HEADER: 6130 { 6131 if (not p_dspin_m2p.write.read()) break; 6132 6133 typedef DspinDhccpParam DDP; 6134 uint64_t header = p_dspin_m2p.data.read(); 6135 uint64_t dest = DDP::dspin_get(header, DDP::TEST_M2P_DEST); 6136 assert((size_t)dest == m_cc_global_id); 6137 6138 r_cc_receive_fsm = CC_RECEIVE_TEST_SIGNATURE; 6139 break; 6140 } 6141 ////////////////////////// 6142 case CC_RECEIVE_TEST_SIGNATURE: 6143 { 6144 if (not p_dspin_m2p.write.read()) break; 6145 assert(not r_cc_test_m2p_req.read()); 6146 r_cc_test_m2p_req = true; 6147 r_cc_test_m2p_sign = p_dspin_m2p.data.read(); 6148 r_cc_receive_fsm = CC_RECEIVE_IDLE; 6149 break; 6150 } 6006 6151 6007 6152 } // end switch CC_RECEIVE FSM … … 6017 6162 size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6018 6163 DspinDhccpParam::CLACK_SET); 6164 6165 size_t clack_test = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6166 DspinDhccpParam::TEST_CLACK_TEST); 6019 6167 6020 6168 bool dspin_clack_get = false; … … 6024 6172 if (r_dspin_clack_req.read()) 6025 6173 { 6174 // CLACK TEST first flit 6175 if (clack_test and not r_dspin_clack_test.read()) 6176 { 6177 r_dspin_clack_test = true; 6178 dspin_clack_get = true; 6179 } 6180 6181 // CLACK TEST second flit 6182 else if (r_dspin_clack_test.read()) 6183 { 6184 assert (not r_cc_test_clack_req.read()); 6185 r_cc_test_clack_req = true; 6186 r_cc_test_clack_sign = r_dspin_clack_flit.read(); 6187 6188 r_dspin_clack_test = false; 6189 dspin_clack_get = true; 6190 } 6191 6026 6192 // CLACK DATA: Send request to DCACHE FSM 6027 if (dcache_clack_request and not r_dcache_clack_req.read())6193 else if (dcache_clack_request and not r_dcache_clack_req.read()) 6028 6194 { 6029 6195 r_dcache_clack_req = true; … … 6053 6219 } 6054 6220 6221 /////////////////////////////////////////////////////////////// 6222 // CC_TEST FSM 6223 /////////////////////////////////////////////////////////////// 6224 6225 // TODO: implement the watchdog timer (reuse the same that for the DATA UNC 6226 // requests?) 6227 const bool watchdog_timeout = false; 6228 6229 switch(r_cc_test_fsm.read()) 6230 { 6231 case CC_TEST_IDLE: 6232 if (not r_dcache_to_cc_test_req.read()) break; 6233 r_cc_test_to_dcache_result = CC_TEST_SUCCESS; 6234 r_cc_test_fsm = CC_TEST_P2M_REQ; 6235 break; 6236 6237 case CC_TEST_P2M_REQ: 6238 assert (not r_cc_test_to_cc_send_req.read()); 6239 r_cc_test_to_cc_send_req = true; 6240 r_cc_test_fsm = CC_TEST_P2M_WAIT; 6241 break; 6242 6243 case CC_TEST_P2M_WAIT: 6244 if (r_cc_test_to_cc_send_req.read()) 6245 { 6246 if (not watchdog_timeout) break; 6247 r_dcache_to_cc_test_req = false; 6248 r_cc_test_to_cc_send_req = false; 6249 r_cc_test_to_dcache_result = CC_TEST_FAILURE; 6250 r_cc_test_fsm = CC_TEST_IDLE; 6251 break; 6252 } 6253 assert (not r_cc_test_clack_req.read() and not r_cc_test_m2p_req.read()); 6254 r_cc_test_fsm = CC_TEST_ACK_WAIT; 6255 break; 6256 6257 case CC_TEST_ACK_WAIT: 6258 if (not r_cc_test_clack_req.read() or not r_cc_test_m2p_req.read()) 6259 { 6260 if (not watchdog_timeout) break; 6261 r_cc_test_to_dcache_result = CC_TEST_FAILURE; 6262 } 6263 6264 // TODO: compare signatures from M2P and CLACK with the sent one 6265 r_dcache_to_cc_test_req = false; 6266 r_cc_test_clack_req = false; 6267 r_cc_test_m2p_req = false; 6268 r_cc_test_fsm = CC_TEST_IDLE; 6269 break; 6270 } 6271 6055 6272 ///////////////// Response FIFOs update ////////////////////// 6056 6273 r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, … … 6063 6280 6064 6281 ///////////////// updt FIFO update ////////////////////// 6065 //TODO check this6066 6282 r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get, 6067 6283 cc_receive_updt_fifo_put, … … 6395 6611 break; 6396 6612 } 6613 /////////////////////// 6614 case CC_SEND_TEST_HEADER: 6615 { 6616 typedef DspinDhccpParam DDP; 6617 uint64_t flit = 0; 6618 6619 uint64_t dest = (uint64_t)r_dcache_to_cc_test_dest.read() 6620 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6621 6622 DDP::dspin_set(flit, DDP::TYPE_TEST, DDP::P2M_TYPE); 6623 DDP::dspin_set(flit, dest, DDP::TEST_P2M_DEST); 6624 DDP::dspin_set(flit, m_cc_global_id, DDP::TEST_P2M_SRCID); 6625 DDP::dspin_set(flit, 1ULL, DDP::TEST_P2M_TEST); 6626 6627 p_dspin_p2m.data = flit; 6628 p_dspin_p2m.write = true; 6629 p_dspin_p2m.eop = false; 6630 break; 6631 } 6632 /////////////////////// 6633 case CC_SEND_TEST_SIGNATURE: 6634 { 6635 typedef DspinDhccpParam DDP; 6636 uint64_t flit = 0; 6637 6638 DDP::dspin_set(flit, r_mmu_word_lo.read(), DDP::TEST_P2M_SIGNATURE); 6639 6640 p_dspin_p2m.data = flit; 6641 p_dspin_p2m.write = true; 6642 p_dspin_p2m.eop = true; 6643 break; 6644 } 6645 6397 6646 } // end switch CC_SEND FSM 6398 6647 … … 6416 6665 case CC_RECEIVE_BRDCAST_NLINE: 6417 6666 { 6418 // TODO maybe we need to wait for both only to leave the state, but6419 // not to actually post a request to an available cache => need a6420 // flip_flop to check that ?6421 6667 if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read())) 6422 6668 p_dspin_m2p.read = true; … … 6481 6727 break; 6482 6728 } 6729 /////////////////////////////// 6730 case CC_RECEIVE_TEST_HEADER: 6731 { 6732 p_dspin_m2p.read = true; 6733 break; 6734 } 6735 /////////////////////////////// 6736 case CC_RECEIVE_TEST_SIGNATURE: 6737 { 6738 p_dspin_m2p.read = true; 6739 break; 6740 } 6483 6741 } // end switch CC_RECEIVE FSM 6484 6742 … … 6486 6744 int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6487 6745 DspinDhccpParam::CLACK_TYPE); 6746 6747 size_t clack_test = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 6748 DspinDhccpParam::TEST_CLACK_TEST); 6488 6749 6489 6750 bool dspin_clack_get = false; … … 6493 6754 if (r_dspin_clack_req.read()) 6494 6755 { 6756 // CLACK TEST 6757 if (clack_test or r_dspin_clack_test.read()) 6758 { 6759 dspin_clack_get = true; 6760 } 6761 6495 6762 // CLACK DATA: wait if pending request to DCACHE FSM 6496 if (dcache_clack_request and not r_dcache_clack_req.read())6763 else if (dcache_clack_request and not r_dcache_clack_req.read()) 6497 6764 { 6498 6765 dspin_clack_get = true;
Note: See TracChangeset
for help on using the changeset viewer.
