Changeset 92 for trunk/platforms/dsx

Timestamp:

Sep 14, 2010, 2:30:25 PM (14 years ago)

Author:

choichil

Message:

Platform with DMA VHDL

Location:

trunk/platforms/dsx/v1_1cluster_phys

Files:

• cluster.py (modified) (2 diffs)
• dsx.conf (modified) (1 diff)
• v1_1cluster_phys.py (modified) (2 diffs)

trunk/platforms/dsx/v1_1cluster_phys/cluster.py

@@ -41 +41 @@
             ('data', 0x10000000, 0x00100000),
             ] )
-        tty  = self.create_tty( addr = 0xc0200000, tty_count = proc_count )
+        tty  = self.create_tty( addr = 0xc0200000, tty_count = 1 )
+        xicu = self.create_xicu( addr = 0xd2200000, pti_count = 1, 
+                                                    hwi_count = 1,
+                                                    wti_count = 4, 
+                                                    irq_count = 4)
+        tty.irq[0] // xicu.hwi[0]
+        for i in range(proc_count):
+            self.cpu[i].irq[0] // xicu.irq[i]
 
     def create_tty(self, addr, tty_count = 1):
@@ -51 +58 @@
         return tty
     
+    def create_xicu(self, addr, pti_count, hwi_count, wti_count, irq_count):
+        name = 'xicu'
+        xicu = self.pf.create('caba:vci_xicu_vhdl', name, pti_count = pti_count,
+                                                          hwi_count = hwi_count,
+                                                          wti_count = wti_count,
+                                                          irq_count = irq_count)
+        self.ringp.to_target.new() // xicu.vci
+        xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False)
+        return xicu
+
 
 class ClusterV3(Cluster):

trunk/platforms/dsx/v1_1cluster_phys/dsx.conf

@@ -1 @@
-soclib_type = "systemc_64"
+soclib_type = "modelsim"

trunk/platforms/dsx/v1_1cluster_phys/v1_1cluster_phys.py

@@ -5 +5 @@
 import soclib.component
 import os
+
+import platform_handlers
 
 class Platform:
@@ -95 +97 @@
     hard = Platform(ClusterV3, cpus, binaries = ["bin.soft"])
     hard.simulator('.')
-#    hard.dts(os.path.basename(__file__)[:-2]+'dts')
-#    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
+    hard.dts(os.path.basename(__file__)[:-2]+'dts')
+    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
 
 if __name__ == '__main__':