Changeset 923
- Timestamp:
- Jan 13, 2015, 9:23:15 AM (10 years ago)
- Location:
- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r919 r923 280 280 MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 281 281 MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access 282 MMU_ READ_DATA_TIMEOUT = 0x1200, // Read &Watchdog timeout282 MMU_WDT_TIMEOUT = 0x1200, // Watchdog timeout 283 283 }; 284 284 … … 600 600 // CC_TEST FSM REGISTER 601 601 /////////////////////////////////// 602 enum cc_test_result_e603 {604 CC_TEST_SUCCESS = 0,605 CC_TEST_FAILURE = 1,606 };607 602 608 603 sc_signal<int> r_cc_test_fsm; … … 612 607 sc_signal<bool> r_cc_test_clack_req; 613 608 sc_signal<uint64_t> r_cc_test_clack_sign; 614 sc_signal<int> r_cc_test_to_dcache_result;615 609 616 610 ////////////////////////////////////////////////////////////////// -
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r919 r923 429 429 r_cc_test_clack_req("r_cc_test_clack_req"), 430 430 r_cc_test_clack_sign("r_cc_test_clack_sign"), 431 r_cc_test_to_dcache_result("r_cc_test_to_dcache_result"),432 431 433 432 r_iss(this->name(), proc_id), … … 2257 2256 m_drsp.rdata = 0; 2258 2257 2258 // watchdog timeout default value 2259 bool dcache_watchdog_timeout = false; 2260 2259 2261 switch (r_dcache_fsm.read()) 2260 2262 { … … 2571 2573 break; 2572 2574 2573 case XTN_CC_TEST:2574 m_drsp.rdata = r_cc_test_to_dcache_result.read();2575 m_drsp.valid = true;2576 m_drsp.error = false;2577 break;2578 2579 2575 default: 2580 2576 r_mmu_detr = MMU_READ_UNDEFINED_XTN; … … 2725 2721 r_dcache_to_cc_test_dest = m_dreq.wdata; 2726 2722 r_dcache_to_cc_test_req = true; 2723 r_dcache_wdt = 0; 2727 2724 r_dcache_fsm = DCACHE_XTN_CC_TEST; 2728 2725 break; … … 4184 4181 } 4185 4182 4183 // increment watchdog timer for black-hole detection 4184 r_dcache_wdt = r_dcache_wdt.read() + 1; 4185 if (r_dcache_wdt.read() == r_dcache_wdt_max.read()) 4186 { 4187 dcache_watchdog_timeout = true; 4188 4189 // TODO: send the TRDID in the coherence packet to detect an early 4190 // WDT timeout 4191 // debug: this counter is used to detect an early WDT timeout. 4192 // It is sent as the data uncacheable transactions TRDID. When a 4193 // response is treated by the RSP FSM, the RTRDID is compared to 4194 // this counter to determine if a timeout was triggered during the 4195 // transaction. 4196 r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1; 4197 4198 #if DEBUG_DCACHE 4199 if (m_debug_dcache_fsm) 4200 { 4201 std::cout << " <PROC " << name() << " DCACHE_XTN_CC_TEST>" 4202 " watchdog timer exception" << std::endl; 4203 } 4204 #endif 4205 } 4206 4186 4207 // wait the CC_TEST request to finish 4187 // the test result is stored at the r_cc_test_to_dcache_result 4188 if (not r_dcache_to_cc_test_req.read()) 4189 { 4208 if (not r_dcache_to_cc_test_req.read() or dcache_watchdog_timeout) 4209 { 4210 if (dcache_watchdog_timeout) 4211 { 4212 r_mmu_detr = MMU_WDT_TIMEOUT; 4213 m_drsp.error = true; 4214 } 4215 m_drsp.valid = true; 4216 4190 4217 r_dcache_fsm = DCACHE_IDLE; 4191 m_drsp.valid = true;4192 4193 4218 #if DEBUG_DCACHE 4194 4219 if (m_debug_dcache_fsm) … … 4198 4223 << std::hex 4199 4224 << " / DEST = " << r_dcache_to_cc_test_dest.read() 4200 << " / RESULt = " << r_cc_test_to_dcache_result.read()4225 << " / TIMEOUT = " << dcache_watchdog_timeout 4201 4226 << std::dec << std::endl; 4202 4227 } … … 4392 4417 if (r_dcache_wdt.read() == r_dcache_wdt_max.read()) 4393 4418 { 4394 r_mmu_detr = MMU_ READ_DATA_TIMEOUT;4419 r_mmu_detr = MMU_WDT_TIMEOUT; 4395 4420 r_mmu_dbvar = r_dcache_save_vaddr.read(); 4396 4421 m_drsp.valid = true; … … 4636 4661 if (r_dcache_wdt.read() == r_dcache_wdt_max.read()) 4637 4662 { 4638 r_mmu_detr = MMU_ READ_DATA_TIMEOUT;4663 r_mmu_detr = MMU_WDT_TIMEOUT; 4639 4664 r_mmu_dbvar = m_dreq.addr; 4640 4665 m_drsp.valid = true; … … 6223 6248 /////////////////////////////////////////////////////////////// 6224 6249 6225 // TODO: implement the watchdog timer (reuse the same that for the DATA UNC6226 // requests?)6227 const bool watchdog_timeout = false;6228 6229 6250 switch(r_cc_test_fsm.read()) 6230 6251 { 6231 6252 case CC_TEST_IDLE: 6232 6253 if (not r_dcache_to_cc_test_req.read()) break; 6233 r_cc_test_to_dcache_result = CC_TEST_SUCCESS;6234 6254 r_cc_test_fsm = CC_TEST_P2M_REQ; 6235 6255 break; … … 6244 6264 if (r_cc_test_to_cc_send_req.read()) 6245 6265 { 6246 if (not watchdog_timeout) break;6266 if (not dcache_watchdog_timeout) break; 6247 6267 r_dcache_to_cc_test_req = false; 6248 6268 r_cc_test_to_cc_send_req = false; 6249 r_cc_test_to_dcache_result = CC_TEST_FAILURE;6250 6269 r_cc_test_fsm = CC_TEST_IDLE; 6251 6270 break; … … 6258 6277 if (not r_cc_test_clack_req.read() or not r_cc_test_m2p_req.read()) 6259 6278 { 6260 if (not watchdog_timeout) break; 6261 r_cc_test_to_dcache_result = CC_TEST_FAILURE; 6279 if (not dcache_watchdog_timeout) break; 6262 6280 } 6263 6281
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