Index: trunk/platforms/tsar_generic_leti/top.cpp
===================================================================
--- trunk/platforms/tsar_generic_leti/top.cpp	(revision 897)
+++ trunk/platforms/tsar_generic_leti/top.cpp	(revision 937)
@@ -3,5 +3,5 @@
 // Author: Alain Greiner
 // Copyright: UPMC/LIP6
-// Date : february 2014
+// Date : february 2013 / updated january 2015
 // This program is released under the GNU public license
 /////////////////////////////////////////////////////////////////////////
@@ -13,22 +13,36 @@
 // (this is defined in the tsar_xbar_cluster).
 //
-// It does not use an external ROM, as the boot code is (pre)loaded
-// in cluster (0,0) memory at address 0x0.
+// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
+// and the number of processors per cluster (NB_PROCS_MAX).
+// The NB_PROCS_MAX parameter cannot be larger than 4.
+//
+// All external peripherals are located in cluster[X_SIZE-1][Y_SIZE-1],
+// and are connected to an IO bus (implemented as a vci_local_crossbar):
+// - one disk controller
+// - one multi-channel ethernet controller
+// - one multi-channel chained buffer dma controller
+// - one multi-channel tty controller
+// - one frame buffer controller
+// - one iopic controller
+// This IO bus is directly connected to the north ports of the CMD/RSP
+// routers in cluster[X_SIZE-1][y_SIZE-2] through VCI/DSPIN wrappers.
+// All other clusters in the upper row are empty: no processors,
+// no ram, no routers. 
+// The X_SIZE parameter must be larger than 0, but no larger than 16.
+// The Y_SIZE parameter must be larger than 1, but no larger than 16.
+//
+// We don't use an external ROM, as the boot code is (pre)loaded
+// in RAM in cluster[0][0] at address 0x0.
+//
+// An optional RAMDISK of 32 Mbytes can be used in RAM of cluster[0][0].
 //
 // The physical address space is 40 bits.
 // The 8 address MSB bits define the cluster index.
 //
-// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
-// and the number of processors per cluster (NB_PROCS_MAX).
-// The number of clusters cannot be larger than 128.
-// The number of processors per cluster cannot be larger than 4.
-//
-// Each cluster contains:
-// - 5 dspin_local_crossbar (local interconnect)
-// - 5 dspin_router (global interconnect)
-// - up to 4 vci_cc_vcache wrapping a MIPS32 processor
+// Besides the processors, each cluster contains:
+// - 5 L1/L2 DSPIN routers implementing 5 separated NOCs
 // - 1 vci_mem_cache
 // - 1 vci_xicu
-// - 1 vci_simple_ram (to model the L3 cache).
+// - 1 vci_simple_ram (to emulate the L3 cache).
 //
 // Each processor receives 4 consecutive IRQ lines from the local XICU.
@@ -36,19 +50,4 @@
 // In all clusters, the MEMC IRQ line (signaling a late write error)
 // is connected to XICU HWI[8]
-// The cluster (0,0) contains two "backup" peripherals:
-// - one block device controller, whose IRQ is connected to XICU HWI[9].
-// - one single channel TTY controller, whose IRQ is connected to XICU HWI[10].
-//
-// The cluster internal architecture is defined in file tsar_leti_cluster,
-// that must be considered as an extension of this top.cpp file.
-//
-// Besides the hardware components in clusters, "external" peripherals
-// are connected to an external IO bus (implemented as a vci_local_crossbar):
-// - one disk controller
-// - one multi-channel ethernet controller
-// - one multi-channel chained buffer dma controller
-// - one multi-channel tty controller
-// - one frame buffer controller
-// - one 32 channels iopic controller
 //
 // This IOBUS is connected to the north  port of the DIR_CMD
@@ -63,4 +62,7 @@
 // - IOPIC HWI[23:16]   connected to IRQ_TTY_RX[7:0]]
 // - IOPIC HWI[31:24]   connected to IRQ_TTY_TX[7:0]]
+//
+// The cluster internal architecture is defined in file tsar_leti_cluster,
+// that must be considered as an extension of this top.cpp file.
 ////////////////////////////////////////////////////////////////////////////
 // The following parameters must be defined in the hard_config.h file :
@@ -73,21 +75,15 @@
 // - NB_TTY_CHANNELS  : number of TTY channels in I/O cluster (8 max)
 // - NB_NIC_CHANNELS  : number of NIC channels in I/O cluster (2 max)
+// - FBUF_X_SIZE      : number of pixels per line for frame buffer
+// - FBUF_Y_SIZE      : number of lines for frame buffer
 //
 // Some other hardware parameters are not used when compiling the OS,
 // and are only defined in this top.cpp file:
 // - XRAM_LATENCY     : external ram latency
-// - MEMC_WAYS        : L2 cache number of ways
-// - MEMC_SETS        : L2 cache number of sets
 // - L1_IWAYS         : L1 cache instruction number of ways
 // - L1_ISETS         : L1 cache instruction number of sets
 // - L1_DWAYS         : L1 cache data number of ways
 // - L1_DSETS         : L1 cache data number of sets
-// - FBUF_X_SIZE      : width of frame buffer (pixels)
-// - FBUF_Y_SIZE      : heigth of frame buffer (lines)
-// - BDEV_IMAGE_NAME  : file pathname for block device
-// - NIC_RX_NAME      : file pathname for NIC received packets
-// - NIC_TX_NAME      : file pathname for NIC transmited packets
-// - NIC_MAC4         : MAC address
-// - NIC_MAC2         : MAC address
+// - BDEV_IMAGE_NAME  : pathname for block device disk image
 /////////////////////////////////////////////////////////////////////////
 // General policy for 40 bits physical address decoding:
@@ -168,11 +164,10 @@
 
 
-/////////////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////////////////////////////////
 //    Secondary Hardware Parameters
-/////////////////////////////////////////////////////////////////////////////////////////
-
-#define MAX_TTY_CHANNELS      8
-#define MAX_CMA_CHANNELS      4
-#define MAX_NIC_CHANNELS      2
+///////////////////////////////////////////////////////////////////////////////////////
+
+#define XMAX                  X_SIZE         // actual number of columns in 2D mesh
+#define YMAX                  (Y_SIZE - 1)   // actual number of rows in 2D mesh
 
 #define XRAM_LATENCY          0
@@ -187,8 +182,7 @@
 #define L1_DSETS              64
 
-#define NIC_MAC4              0XBABEF00D
-#define NIC_MAC2              0xBEEF
-#define NIC_RX_NAME           "/dev/null"
-#define NIC_TX_NAME           "/dev/null"
+#define BDEV_IMAGE_NAME       "../../../giet_vm/hdd/virt_hdd.dmg"
+
+#define ROM_SOFT_NAME         "../../softs/tsar_boot/preloader.elf"
 
 #define NORTH                 0
@@ -230,15 +224,15 @@
    using namespace soclib::common;
 
-   uint32_t ncycles           = 0xFFFFFFFF; // max simulated cycles
-   size_t   threads           = 1;          // simulator's threads number
-   bool     trace_ok          = false;      // trace activated
-   uint32_t trace_from        = 0;          // trace start cycle
-   bool     trace_proc_ok     = false;      // detailed proc trace activated
-   size_t   trace_memc_ok     = false;      // detailed memc trace activated
-   size_t   trace_memc_id     = 0;          // index of memc to be traced
-   size_t   trace_proc_id     = 0;          // index of proc to be traced
-   uint32_t frozen_cycles     = MAX_FROZEN_CYCLES;
-   char     soft_name[256]    = "soft.elf";
-   char     disk_name[256]    = "disk.img";
+   uint32_t ncycles           = 0xFFFFFFFF;         // max simulated cycles
+   size_t   threads           = 1;                  // simulator's threads number
+   bool     trace_ok          = false;              // trace activated
+   uint32_t trace_from        = 0;                  // trace start cycle
+   bool     trace_proc_ok     = false;              // detailed proc trace activated
+   size_t   trace_memc_ok     = false;              // detailed memc trace activated
+   size_t   trace_memc_id     = 0;                  // index of memc to be traced
+   size_t   trace_proc_id     = 0;                  // index of proc to be traced
+   char     soft_name[256]    = ROM_SOFT_NAME;      // pathname for ROM binary code
+   char     disk_name[256]    = BDEV_IMAGE_NAME;    // pathname for DISK image
+   uint32_t frozen_cycles     = MAX_FROZEN_CYCLES;  // for debug
    struct   timeval t1,t2;
    uint64_t ms1,ms2;
@@ -265,5 +259,5 @@
             size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
 
-            assert( (x < X_SIZE) and (y < (Y_SIZE)) and
+            assert( (x < XMAX) and (y < (YMAX)) and
                   "MEMCID parameter refers a not valid memory cache");
          }
@@ -277,8 +271,8 @@
             size_t l          = trace_proc_id & ((1<<P_WIDTH)-1) ;
 
-            assert( (x < X_SIZE) and (y < Y_SIZE) and (l < NB_PROCS_MAX) and
+            assert( (x < XMAX) and (y < YMAX) and (l < NB_PROCS_MAX) and
                   "PROCID parameter refers a not valid processor");
          }
-         else if ((strcmp(argv[n], "-SOFT") == 0) && ((n + 1) < argc))
+         else if ((strcmp(argv[n], "-ROM") == 0) && ((n + 1) < argc))
          {
             strcpy(soft_name, argv[n + 1]);
@@ -302,13 +296,13 @@
             std::cout << "   The order is not important." << std::endl;
             std::cout << "   Accepted arguments are :" << std::endl << std::endl;
-            std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
-            std::cout << "     -DEBUG debug_start_cycle" << std::endl;
-            std::cout << "     -SOFT path to soft" << std::endl;
-            std::cout << "     -DISK path to disk image" << std::endl;
-            std::cout << "     -THREADS simulator's threads number" << std::endl;
-            std::cout << "     -FROZEN max_number_of_lines" << std::endl;
-            std::cout << "     -PERIOD number_of_cycles between trace" << std::endl;
-            std::cout << "     -MEMCID index_memc_to_be_traced" << std::endl;
-            std::cout << "     -PROCID index_proc_to_be_traced" << std::endl;
+            std::cout << "     - NCYCLES number_of_simulated_cycles" << std::endl;
+            std::cout << "     - DEBUG debug_start_cycle" << std::endl;
+            std::cout << "     - ROM path to ROM image" << std::endl;
+            std::cout << "     - DISK path to disk image" << std::endl;
+            std::cout << "     - THREADS simulator's threads number" << std::endl;
+            std::cout << "     - FROZEN max_number_of_lines" << std::endl;
+            std::cout << "     - PERIOD number_of_cycles between trace" << std::endl;
+            std::cout << "     - MEMCID index_memc_to_be_traced" << std::endl;
+            std::cout << "     - PROCID index_proc_to_be_traced" << std::endl;
             exit(0);
          }
@@ -317,9 +311,8 @@
 
     // checking hardware parameters
-    assert( ((X_SIZE==1) or (X_SIZE==2) or (X_SIZE==4) or (X_SIZE==8) or
-             (X_SIZE==16)) and
+    assert( ((X_SIZE <= 16) and (X_SIZE > 0)) and
             "Illegal X_SIZE parameter" );
 
-    assert( ((Y_SIZE==1) or (Y_SIZE==2) or (Y_SIZE==4) or (Y_SIZE==8)) and
+    assert( ((Y_SIZE <= 16) and (Y_SIZE > 1)) and
             "Illegal Y_SIZE parameter" );
 
@@ -330,11 +323,11 @@
             "Illegal NB_PROCS_MAX parameter" );
 
-    assert( (NB_CMA_CHANNELS <= MAX_CMA_CHANNELS) and
+    assert( (NB_CMA_CHANNELS <= 4) and
             "The NB_CMA_CHANNELS parameter cannot be larger than 4" );
 
-    assert( (NB_TTY_CHANNELS <= MAX_TTY_CHANNELS) and
-            "The NB_TTY_CHANNELS parameter cannot be larger than 8" );
-
-    assert( (NB_NIC_CHANNELS <= MAX_NIC_CHANNELS) and
+    assert( (NB_TTY_CHANNELS <= 8) and
+            "The NB_TTY_CHANNELS parameter cannot be larger than 16" );
+
+    assert( (NB_NIC_CHANNELS <= 2) and
             "The NB_NIC_CHANNELS parameter cannot be larger than 2" );
 
@@ -343,14 +336,14 @@
 
     assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
-            "ERROR: you must have X_WIDTH == Y_WIDTH == 4");
+            "You must have X_WIDTH == Y_WIDTH == 4");
 
     std::cout << std::endl;
 
-    std::cout << " - X_SIZE           = " << X_SIZE << std::endl;
-    std::cout << " - Y_SIZE           = " << Y_SIZE << std::endl;
+    std::cout << " - XMAX           = " << XMAX << std::endl;
+    std::cout << " - YMAX           = " << YMAX << std::endl;
     std::cout << " - NB_PROCS_MAX     = " << NB_PROCS_MAX <<  std::endl;
-    std::cout << " - NB_DMA_CHANNELS  = " << NB_DMA_CHANNELS <<  std::endl;
     std::cout << " - NB_TTY_CHANNELS  = " << NB_TTY_CHANNELS <<  std::endl;
     std::cout << " - NB_NIC_CHANNELS  = " << NB_NIC_CHANNELS <<  std::endl;
+    std::cout << " - NB_CMA_CHANNELS  = " << NB_CMA_CHANNELS <<  std::endl;
     std::cout << " - MEMC_WAYS        = " << MEMC_WAYS << std::endl;
     std::cout << " - MEMC_SETS        = " << MEMC_SETS << std::endl;
@@ -405,7 +398,7 @@
 
    // replicated segments
-   for (size_t x = 0; x < X_SIZE; x++)
+   for (size_t x = 0; x < XMAX; x++)
    {
-      for (size_t y = 0; y < (Y_SIZE) ; y++)
+      for (size_t y = 0; y < (YMAX) ; y++)
       {
          sc_uint<vci_address_width> offset;
@@ -436,25 +429,25 @@
                IntTab(cluster(0,0),BDEV_TGTID), false));
 
-   // segments for peripherals in cluster_io (X_SIZE-1,Y_SIZE)
+   // segments for peripherals in cluster_io (XMAX-1,YMAX)
    sc_uint<vci_address_width> offset;
-   offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32;
+   offset = ((sc_uint<vci_address_width>)cluster(XMAX-1,YMAX)) << 32;
 
    maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
-               IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false));
+               IntTab(cluster(XMAX-1, YMAX),MTTY_TGTID), false));
 
    maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
-               IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false));
+               IntTab(cluster(XMAX-1, YMAX),FBUF_TGTID), false));
 
    maptabd.add(Segment("seg_bdev", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
-               IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false));
+               IntTab(cluster(XMAX-1, YMAX),BDEV_TGTID), false));
 
    maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
-               IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false));
+               IntTab(cluster(XMAX-1, YMAX),MNIC_TGTID), false));
 
    maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
-               IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false));
+               IntTab(cluster(XMAX-1, YMAX),CDMA_TGTID), false));
 
    maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
-               IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false));
+               IntTab(cluster(XMAX-1, YMAX),IOPI_TGTID), false));
 
    std::cout << maptabd << std::endl;
@@ -469,7 +462,7 @@
                          0x00FF000000ULL);
 
-    for (size_t x = 0; x < X_SIZE; x++)
-    {
-        for (size_t y = 0; y < (Y_SIZE) ; y++)
+    for (size_t x = 0; x < XMAX; x++)
+    {
+        for (size_t y = 0; y < (YMAX) ; y++)
         {
             sc_uint<vci_address_width> offset;
@@ -498,5 +491,4 @@
     sc_signal<bool>                   signal_irq_mnic_tx[NB_NIC_CHANNELS];
     sc_signal<bool>                   signal_irq_mtty_rx[NB_TTY_CHANNELS];
-//  sc_signal<bool>                   signal_irq_mtty_tx[NB_TTY_CHANNELS];
     sc_signal<bool>                   signal_irq_cdma[NB_CMA_CHANNELS];
     sc_signal<bool>                   signal_irq_false;
@@ -504,79 +496,79 @@
    // Horizontal inter-clusters DSPIN signals
    DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX);
    DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX);
 
    DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX);
    DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX);
 
    DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", XMAX-1, YMAX);
    DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", XMAX-1, YMAX);
 
    DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", XMAX-1, YMAX);
    DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", XMAX-1, YMAX);
 
    DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", XMAX-1, YMAX);
    DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", XMAX-1, YMAX);
 
    // Vertical inter-clusters DSPIN signals
    DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1);
    DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1);
 
    DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1);
    DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1);
 
    DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", XMAX, YMAX-1);
    DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", XMAX, YMAX-1);
 
    DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", XMAX, YMAX-1);
    DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", XMAX, YMAX-1);
 
    DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", XMAX, YMAX-1);
    DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", XMAX, YMAX-1);
 
    // Mesh boundaries DSPIN signals (Most of those signals are not used...)
    DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , XMAX, YMAX, 4);
    DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", XMAX, YMAX, 4);
 
    DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , XMAX, YMAX, 4);
    DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", XMAX, YMAX, 4);
 
    DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , XMAX, YMAX, 4);
    DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", XMAX, YMAX, 4);
 
    DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , XMAX, YMAX, 4);
    DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
-      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", XMAX, YMAX, 4);
 
    DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , XMAX, YMAX, 4);
    DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
-      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4);
+      alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", XMAX, YMAX, 4);
 
    // VCI signals for iobus and peripherals
@@ -611,9 +603,6 @@
    soclib::common::Loader loader( soft_name );
 #endif
+
    loader.memory_default(0xAA);
-
-   ///////////////////////////
-   //  processor iss
-   ///////////////////////////
 
    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
@@ -621,5 +610,5 @@
 
    //////////////////////////////////////////////////////////////
-   // mesh construction: only (X_SIZE) * (Y_SIZE) clusters
+   // mesh construction: XMAX * YMAX clusters
    //////////////////////////////////////////////////////////////
 
@@ -627,5 +616,5 @@
                    dspin_rsp_width,
                    vci_param_int,
-                   vci_param_ext>*          clusters[X_SIZE][Y_SIZE];
+                   vci_param_ext>*          clusters[XMAX][YMAX];
 
 #if USE_OPENMP
@@ -634,8 +623,8 @@
 #pragma omp for
 #endif
-        for (size_t i = 0; i  < (X_SIZE * (Y_SIZE)); i++)
+        for (size_t i = 0; i  < (XMAX * YMAX); i++)
         {
-            size_t x = i / (Y_SIZE);
-            size_t y = i % (Y_SIZE);
+            size_t x = i / (YMAX);
+            size_t y = i % (YMAX);
 
 #if USE_OPENMP
@@ -697,8 +686,8 @@
 #endif
 
-
 #if USE_PIC
+
     //////////////////////////////////////////////////////////////////
-    // IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE]
+    // IO bus and external peripherals in cluster[X_SIZE-1][Y_SIZE-1]
     // - 6 local targets    : FBF, TTY, CMA, NIC, PIC, IOC
     // - 3 local initiators : IOC, CMA, PIC
@@ -714,5 +703,5 @@
     std::cout << std::endl;
 
-    size_t cluster_io = cluster(X_SIZE-1, Y_SIZE);
+    size_t cluster_io = cluster(XMAX-1, YMAX);
 
     //////////// vci_local_crossbar
@@ -752,8 +741,7 @@
                 maptabd,
                 NB_NIC_CHANNELS,
-                NIC_MAC4,
-                NIC_MAC2,
-                NIC_RX_NAME,
-                NIC_TX_NAME );
+                0,                // default MAC_4 address
+                0,                // default MAC_2 address
+                1 );              // NIC_MODE_SYNTHESIS
 
     ///////////// vci_chbuf_dma
@@ -764,5 +752,5 @@
                 IntTab(cluster_io, CDMA_SRCID),
                 IntTab(cluster_io, CDMA_TGTID),
-                64,                          // burst size
+                64,                               // burst size
                 NB_CMA_CHANNELS );
 
@@ -795,14 +783,14 @@
     VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
     wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
-                "wt_bdev",
+                "wt_iobus",
                 vci_srcid_width );
 
     VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
     wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
-                "wi_bdev",
+                "wi_iobus",
                 vci_srcid_width );
 
     ///////////////////////////////////////////////////////////////
-    //     Net-list
+    //     IObus  Net-list
     ///////////////////////////////////////////////////////////////
 
@@ -887,5 +875,5 @@
     // NB_NIC_CHANNELS <= 2
     // NB_CMA_CHANNELS <= 4
-    // NB_TTY_CHANNELS <= 8
+    // NB_TTY_CHANNELS <= 16
     iopic->p_clk                       (signal_clk);
     iopic->p_resetn                    (signal_resetn);
@@ -903,7 +891,4 @@
        else if(i < 16)                 iopic->p_hwi[i] (signal_irq_false);
        else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
-       else if(i < 24)                 iopic->p_hwi[i] (signal_irq_false);
-       else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false);
-//     else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]);
        else                            iopic->p_hwi[i] (signal_irq_false);
     }
@@ -915,6 +900,6 @@
     wi_iobus->p_resetn                 (signal_resetn);
     wi_iobus->p_vci                    (signal_vci_cmd_to_noc);
-    wi_iobus->p_dspin_cmd              (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]);
-    wi_iobus->p_dspin_rsp              (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]);
+    wi_iobus->p_dspin_cmd              (signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH]);
+    wi_iobus->p_dspin_rsp              (signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH]);
 
     // vci/dspin wrappers
@@ -922,13 +907,13 @@
     wt_iobus->p_resetn                 (signal_resetn);
     wt_iobus->p_vci                    (signal_vci_cmd_from_noc);
-    wt_iobus->p_dspin_cmd              (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]);
-    wt_iobus->p_dspin_rsp              (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]);
-
-#endif // USE_PIC
+    wt_iobus->p_dspin_cmd              (signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH]);
+    wt_iobus->p_dspin_rsp              (signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH]);
+
+#endif  // USE_PIC
 
     // Clock & RESET for clusters
-    for (size_t x = 0; x < (X_SIZE); x++)
-    {
-        for (size_t y = 0; y < (Y_SIZE); y++)
+    for (size_t x = 0; x < (XMAX); x++)
+    {
+        for (size_t y = 0; y < (YMAX); y++)
         {
             clusters[x][y]->p_clk                    (signal_clk);
@@ -938,9 +923,9 @@
 
     // Inter Clusters horizontal connections
-    if (X_SIZE > 1)
-    {
-        for (size_t x = 0; x < (X_SIZE-1); x++)
+    if (XMAX > 1)
+    {
+        for (size_t x = 0; x < (XMAX-1); x++)
         {
-            for (size_t y = 0; y < (Y_SIZE); y++)
+            for (size_t y = 0; y < (YMAX); y++)
             {
                 clusters[x][y]->p_cmd_out[EAST]      (signal_dspin_h_cmd_inc[x][y]);
@@ -974,9 +959,9 @@
 
     // Inter Clusters vertical connections
-    if (Y_SIZE > 1)
-    {
-        for (size_t y = 0; y < (Y_SIZE-1); y++)
+    if (YMAX > 1)
+    {
+        for (size_t y = 0; y < (YMAX-1); y++)
         {
-            for (size_t x = 0; x < X_SIZE; x++)
+            for (size_t x = 0; x < XMAX; x++)
             {
                 clusters[x][y]->p_cmd_out[NORTH]     (signal_dspin_v_cmd_inc[x][y]);
@@ -1010,30 +995,30 @@
 
     // East & West boundary cluster connections
-    for (size_t y = 0; y < (Y_SIZE); y++)
+    for (size_t y = 0; y < (YMAX); y++)
     {
         clusters[0][y]->p_cmd_in[WEST]           (signal_dspin_bound_cmd_in[0][y][WEST]);
         clusters[0][y]->p_cmd_out[WEST]          (signal_dspin_bound_cmd_out[0][y][WEST]);
-        clusters[X_SIZE-1][y]->p_cmd_in[EAST]    (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);
-        clusters[X_SIZE-1][y]->p_cmd_out[EAST]   (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);
+        clusters[XMAX-1][y]->p_cmd_in[EAST]    (signal_dspin_bound_cmd_in[XMAX-1][y][EAST]);
+        clusters[XMAX-1][y]->p_cmd_out[EAST]   (signal_dspin_bound_cmd_out[XMAX-1][y][EAST]);
 
         clusters[0][y]->p_rsp_in[WEST]           (signal_dspin_bound_rsp_in[0][y][WEST]);
         clusters[0][y]->p_rsp_out[WEST]          (signal_dspin_bound_rsp_out[0][y][WEST]);
-        clusters[X_SIZE-1][y]->p_rsp_in[EAST]    (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);
-        clusters[X_SIZE-1][y]->p_rsp_out[EAST]   (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);
+        clusters[XMAX-1][y]->p_rsp_in[EAST]    (signal_dspin_bound_rsp_in[XMAX-1][y][EAST]);
+        clusters[XMAX-1][y]->p_rsp_out[EAST]   (signal_dspin_bound_rsp_out[XMAX-1][y][EAST]);
 
         clusters[0][y]->p_m2p_in[WEST]           (signal_dspin_bound_m2p_in[0][y][WEST]);
         clusters[0][y]->p_m2p_out[WEST]          (signal_dspin_bound_m2p_out[0][y][WEST]);
-        clusters[X_SIZE-1][y]->p_m2p_in[EAST]    (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);
-        clusters[X_SIZE-1][y]->p_m2p_out[EAST]   (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);
+        clusters[XMAX-1][y]->p_m2p_in[EAST]    (signal_dspin_bound_m2p_in[XMAX-1][y][EAST]);
+        clusters[XMAX-1][y]->p_m2p_out[EAST]   (signal_dspin_bound_m2p_out[XMAX-1][y][EAST]);
 
         clusters[0][y]->p_p2m_in[WEST]           (signal_dspin_bound_p2m_in[0][y][WEST]);
         clusters[0][y]->p_p2m_out[WEST]          (signal_dspin_bound_p2m_out[0][y][WEST]);
-        clusters[X_SIZE-1][y]->p_p2m_in[EAST]    (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);
-        clusters[X_SIZE-1][y]->p_p2m_out[EAST]   (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);
+        clusters[XMAX-1][y]->p_p2m_in[EAST]    (signal_dspin_bound_p2m_in[XMAX-1][y][EAST]);
+        clusters[XMAX-1][y]->p_p2m_out[EAST]   (signal_dspin_bound_p2m_out[XMAX-1][y][EAST]);
 
         clusters[0][y]->p_cla_in[WEST]           (signal_dspin_bound_cla_in[0][y][WEST]);
         clusters[0][y]->p_cla_out[WEST]          (signal_dspin_bound_cla_out[0][y][WEST]);
-        clusters[X_SIZE-1][y]->p_cla_in[EAST]    (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);
-        clusters[X_SIZE-1][y]->p_cla_out[EAST]   (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);
+        clusters[XMAX-1][y]->p_cla_in[EAST]    (signal_dspin_bound_cla_in[XMAX-1][y][EAST]);
+        clusters[XMAX-1][y]->p_cla_out[EAST]   (signal_dspin_bound_cla_out[XMAX-1][y][EAST]);
     }
 
@@ -1041,30 +1026,30 @@
 
     // North & South boundary clusters connections
-    for (size_t x = 0; x < X_SIZE; x++)
+    for (size_t x = 0; x < XMAX; x++)
     {
         clusters[x][0]->p_cmd_in[SOUTH]          (signal_dspin_bound_cmd_in[x][0][SOUTH]);
         clusters[x][0]->p_cmd_out[SOUTH]         (signal_dspin_bound_cmd_out[x][0][SOUTH]);
-        clusters[x][Y_SIZE-1]->p_cmd_in[NORTH]   (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);
-        clusters[x][Y_SIZE-1]->p_cmd_out[NORTH]  (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);
+        clusters[x][YMAX-1]->p_cmd_in[NORTH]   (signal_dspin_bound_cmd_in[x][YMAX-1][NORTH]);
+        clusters[x][YMAX-1]->p_cmd_out[NORTH]  (signal_dspin_bound_cmd_out[x][YMAX-1][NORTH]);
 
         clusters[x][0]->p_rsp_in[SOUTH]          (signal_dspin_bound_rsp_in[x][0][SOUTH]);
         clusters[x][0]->p_rsp_out[SOUTH]         (signal_dspin_bound_rsp_out[x][0][SOUTH]);
-        clusters[x][Y_SIZE-1]->p_rsp_in[NORTH]   (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);
-        clusters[x][Y_SIZE-1]->p_rsp_out[NORTH]  (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);
+        clusters[x][YMAX-1]->p_rsp_in[NORTH]   (signal_dspin_bound_rsp_in[x][YMAX-1][NORTH]);
+        clusters[x][YMAX-1]->p_rsp_out[NORTH]  (signal_dspin_bound_rsp_out[x][YMAX-1][NORTH]);
 
         clusters[x][0]->p_m2p_in[SOUTH]          (signal_dspin_bound_m2p_in[x][0][SOUTH]);
         clusters[x][0]->p_m2p_out[SOUTH]         (signal_dspin_bound_m2p_out[x][0][SOUTH]);
-        clusters[x][Y_SIZE-1]->p_m2p_in[NORTH]   (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);
-        clusters[x][Y_SIZE-1]->p_m2p_out[NORTH]  (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);
+        clusters[x][YMAX-1]->p_m2p_in[NORTH]   (signal_dspin_bound_m2p_in[x][YMAX-1][NORTH]);
+        clusters[x][YMAX-1]->p_m2p_out[NORTH]  (signal_dspin_bound_m2p_out[x][YMAX-1][NORTH]);
 
         clusters[x][0]->p_p2m_in[SOUTH]          (signal_dspin_bound_p2m_in[x][0][SOUTH]);
         clusters[x][0]->p_p2m_out[SOUTH]         (signal_dspin_bound_p2m_out[x][0][SOUTH]);
-        clusters[x][Y_SIZE-1]->p_p2m_in[NORTH]   (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);
-        clusters[x][Y_SIZE-1]->p_p2m_out[NORTH]  (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);
+        clusters[x][YMAX-1]->p_p2m_in[NORTH]   (signal_dspin_bound_p2m_in[x][YMAX-1][NORTH]);
+        clusters[x][YMAX-1]->p_p2m_out[NORTH]  (signal_dspin_bound_p2m_out[x][YMAX-1][NORTH]);
 
         clusters[x][0]->p_cla_in[SOUTH]          (signal_dspin_bound_cla_in[x][0][SOUTH]);
         clusters[x][0]->p_cla_out[SOUTH]         (signal_dspin_bound_cla_out[x][0][SOUTH]);
-        clusters[x][Y_SIZE-1]->p_cla_in[NORTH]   (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);
-        clusters[x][Y_SIZE-1]->p_cla_out[NORTH]  (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);
+        clusters[x][YMAX-1]->p_cla_in[NORTH]   (signal_dspin_bound_cla_in[x][YMAX-1][NORTH]);
+        clusters[x][YMAX-1]->p_cla_out[NORTH]  (signal_dspin_bound_cla_out[x][YMAX-1][NORTH]);
     }
 
@@ -1083,11 +1068,11 @@
     // set network boundaries signals default values
     // for all boundary clusters but the IO cluster
-    for (size_t x = 0; x < X_SIZE ; x++)
-    {
-        for (size_t y = 0; y < Y_SIZE ; y++)
+    for (size_t x = 0; x < XMAX ; x++)
+    {
+        for (size_t y = 0; y < YMAX ; y++)
         {
             for (size_t face = 0; face < 4; face++)
             {
-                if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) )
+                if ( (x != XMAX-1) or (y != YMAX-1) or (face != NORTH) )
                 {
                     signal_dspin_bound_cmd_in [x][y][face].write = false;
@@ -1121,8 +1106,8 @@
 
 #if USE_PIC == 0
-    signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH].write = false;
-    signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH].read = true;
-    signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH].read = true;
-    signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH].write = false;
+    signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH].write = false;
+    signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH].read = true;
+    signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH].read = true;
+    signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH].write = false;
 #endif
 
@@ -1141,22 +1126,15 @@
     }
 
-#if USE_PIC
-    // variable used for IRQ trace
-    bool prev_irq_bdev = false;
-    bool prev_irq_mtty_rx[8];
-    bool prev_irq_proc[16][16][4];
-
-    for( size_t x = 0 ; x<8  ; x++ ) prev_irq_mtty_rx[x] = false;
-
-    for( size_t x = 0 ; x<16 ; x++ )
-    for( size_t y = 0 ; y<16 ; y++ )
-    for( size_t i = 0 ; i<4  ; i++ ) prev_irq_proc[x][y][i] = false;
-#endif
-
+    // simulation loop
     for (uint64_t n = 1; n < ncycles && !stop_called; n++)
     {
-        // Monitor a specific address for L1 & L2 caches
+        // Monitor a specific address for L1 cache
         // clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
-        // clusters[1][1]->memc->cache_monitor(0x110002c078ULL);
+
+        // Monitor a specific address for L2 cache
+        // clusters[1][1]->memc->cache_monitor(0x200000F000ULL);
+
+        // Monitor a specific address for one XRAM
+        // clusters[0][0]->xram->start_monitor( 0x200000F00ULL , 64);
 
         // stats display
@@ -1186,5 +1164,5 @@
         {
             std::cout << "****************** cycle " << std::dec << n ;
-            std::cout << " ************************************************" << std::endl;
+            std::cout << " ********************************************" << std::endl;
 
             size_t l = 0;
@@ -1207,4 +1185,13 @@
                 clusters[x][y]->xicu->print_trace(0);
                 clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
+                
+                if ( clusters[x][y]->signal_proc_irq[0] ) 
+                   std::cout << "### IRQ_PROC_" << x << "_" << y << "_0" << std::endl;
+                if ( clusters[x][y]->signal_proc_irq[4] ) 
+                   std::cout << "### IRQ_PROC_" << x << "_" << y << "_1" << std::endl;
+                if ( clusters[x][y]->signal_proc_irq[8] ) 
+                   std::cout << "### IRQ_PROC_" << x << "_" << y << "_2" << std::endl;
+                if ( clusters[x][y]->signal_proc_irq[12] ) 
+                   std::cout << "### IRQ_PROC_" << x << "_" << y << "_3" << std::endl;
             }
 
@@ -1257,4 +1244,7 @@
             signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
             signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
+
+            // trace external interrupts
+            if (signal_irq_bdev)   std::cout << "### IRQ_BDEV" << std::endl;
 #else
             clusters[0][0]->bdev->print_trace();
@@ -1263,52 +1253,5 @@
 #endif
 
-            // trace internal tty
-            // clusters[0][0]->mtty->print_trace();
-            // clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY");
-
         }  // end trace
-
-#if 0
-#if USE_PIC
-        // trace BDV interrupts events
-        if ( signal_irq_bdev.read() != prev_irq_bdev )
-        {
-           prev_irq_bdev = signal_irq_bdev.read();
-           std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read()
-              << " at cycle " << n << std::endl;
-        }
-
-        // trace TTY interrupts events
-        for ( size_t x = 0 ; x < 8 ; x++ )
-        {
-           if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] )
-           {
-              prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read();
-              std::cout << std::dec << "@@@ IRQ_MTTY["<<x<<"] = "
-                 << signal_irq_mtty_rx[x].read()
-                 << " at cycle " << n << std::endl;
-           }
-        }
-        // trace VCI transactions on IOPIC and XCU(0,0)
-        signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT");
-        signal_vci_ini_iopi.print_trace("@@@ IOPI_INI");
-#endif
-
-        // trace processor interrupts events
-        for ( size_t x = 0 ; x < X_SIZE ; x++ )
-           for ( size_t y = 0 ; y < Y_SIZE ; y++ )
-              for ( size_t i = 0 ; i < NB_PROCS_MAX ; i++ )
-              {
-                 if ( clusters[x][y]->signal_proc_irq[i] != prev_irq_proc[x][y][i] )
-                 {
-                    prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i];
-                    std::cout << std::dec << "@@@ IRQ_PROC["<<x<<","<<y<<","<<i<<"] = "
-                       << clusters[x][y]->signal_proc_irq[i]
-                       << " at cycle " << n << std::endl;
-                 }
-              }
-
-        clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0");
-#endif
 
         sc_start(sc_core::sc_time(1, SC_NS));
