Index: /trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.cpp
===================================================================
--- /trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.cpp	(revision 93)
+++ /trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.cpp	(revision 94)
@@ -5,5 +5,5 @@
  ** your changes will be lost !
  **
- ** Generated by DSX on 2010-09-14 14:36:17.463123
+ ** Generated by DSX on 2010-09-14 15:19:49.691098
  ** by choichil@hop
  ** MARKER_END
@@ -1212,19 +1212,19 @@
 {
     // Segment configure;
-    mtc.add(proc_0_1_seg);
     mtc.add(ram_c_reset_seg);
     mtc.add(ram_c_excep_seg);
     mtc.add(ram_c_text_seg);
     mtc.add(ram_c_data_seg);
+    mtc.add(proc_0_3_seg);
     mtc.add(proc_0_0_seg);
+    mtc.add(proc_0_1_seg);
     mtc.add(proc_0_2_seg);
-    mtc.add(proc_0_3_seg);
+    mtp.add(xicu_seg);
     mtp.add(tty0_seg);
+    mtp.add(dma0_seg);
     mtp.add(ram_p_reset_seg);
     mtp.add(ram_p_excep_seg);
     mtp.add(ram_p_text_seg);
     mtp.add(ram_p_data_seg);
-    mtp.add(xicu_seg);
-    mtp.add(dma0_seg);
     mtx.add(ram_x_reset_seg);
     mtx.add(ram_x_excep_seg);
Index: /trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.sd
===================================================================
--- /trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.sd	(revision 93)
+++ /trunk/platforms/dsx/v1_1cluster_phys_dma/topcell_/topcell_.sd	(revision 94)
@@ -5,5 +5,5 @@
 # your changes will be lost !
 #
-## Generated by DSX on 2010-09-14 14:36:17.024238
+## Generated by DSX on 2010-09-14 15:19:49.271489
 ## by choichil@hop
 ## MARKER_END
@@ -29,6 +29,6 @@
 		Uses('common:plain_file_loader', )],
 	header_files = ['topcell_.h'],
-	ports = [Port("caba:bit_in", "p_resetn", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1),
-		Port("caba:clock_in", "p_clock", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1)],
+	ports = [Port("caba:clock_in", "p_clock", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1),
+		Port("caba:bit_in", "p_resetn", addr_size = 64, cell_size = 4, clen_size = 1, pktid_size = 4, plen_size = 8, rerror_size = 1, rflag_size = 1, srcid_size = 14, trdid_size = 4, wrplen_size = 1)],
 	implementation_files = ['topcell_.cpp']
 )