Index: /trunk/platforms/tsar_generic_mwmr/Makefile =================================================================== --- /trunk/platforms/tsar_generic_mwmr/Makefile (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/Makefile (revision 956) @@ -0,0 +1,9 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x tty* term* + +.PHONY:simul.x + Index: /trunk/platforms/tsar_generic_mwmr/arch.py =================================================================== --- /trunk/platforms/tsar_generic_mwmr/arch.py (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/arch.py (revision 956) @@ -0,0 +1,429 @@ +#!/usr/bin/env python + +from math import log, ceil +from mapping import * + +################################################################################## +# file : arch.py (for the tsar_generic_mwmr architecture) +# date : may 2014 +# author : Alain Greiner +################################################################################## +# This file contains a mapping generator for the "tsar_generic_mwmr" platform. +# This includes both the hardware architecture (clusters, processors, peripherals, +# physical space segmentation) and the mapping of all boot and kernel objects +# (global vsegs). +# +# This platform includes 6 external peripherals, accessible through an IOB +# components located in cluster [0,0] or in cluster [x_size-1, y_size-1]. +# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA, PIC. +# +# All clusters contain (nb_procs) processors, one L2 cache, one XCU, and +# one MWMR-DMA controller. +# +# The "constructor" parameters are: +# - x_size : number of clusters in a row +# - y_size : number of clusters in a column +# - nb_procs : number of processors per cluster +# - nb_ttys : number of TTY channels +# - fbf_width : frame_buffer width = frame_buffer heigth +# +# The other hardware parameters are: +# - nb_nics : number of NIC channels +# - nb_cmas : number of CMA channels +# - x_io : cluster_io x coordinate +# - y_io : cluster_io y coordinate +# - x_width : number of bits for x coordinate +# - y_width : number of bits for y coordinate +# - paddr_width : number of bits for physical address +# - irq_per_proc : number of input IRQs per processor +# - use_ramdisk : use a ramdisk when True +# - vseg_increment : address increment for replicated peripherals +# +# Regarding the boot and kernel vsegs mapping : +# - We use one big physical page (2 Mbytes) for the preloader and the four +# boot vsegs, all allocated in cluster[0,0]. +# - We use one big page per cluster for the replicated kernel code vsegs. +# - We use one big page in cluster[0][0] for the kernel data vseg. +# - We use one big page per cluster for the distributed kernel heap vsegs. +# - We use one big page per cluster for the distributed ptab vsegs. +# - We use small physical pages (4 Kbytes) per cluster for the schedulers. +# - We use one big page for each external peripheral in IO cluster, +# - We use one small page per cluster for each internal peripheral. +################################################################################## + +######################## +def arch( x_size = 2, + y_size = 2, + nb_procs = 2, + nb_ttys = 1, + fbf_width = 128 ): + + ### define architecture constants + + nb_nics = 1 + nb_cmas = 2 + x_io = 0 + y_io = 0 + x_width = 4 + y_width = 4 + p_width = 4 + paddr_width = 40 + irq_per_proc = 4 + use_ramdisk = False + peri_increment = 0x10000 # distributed peripherals vbase address increment + + ### parameters checking + + assert( nb_procs <= (1 << p_width) ) + + assert( (x_size == 1) or (x_size == 2) or (x_size == 4) + or (x_size == 8) or (x_size == 16) ) + + assert( (y_size == 1) or (y_size == 2) or (y_size == 4) + or (y_size == 8) or (y_size == 16) ) + + assert( (nb_ttys >= 1) and (nb_ttys <= 8) ) + + assert( ((x_io == 0) and (y_io == 0)) or + ((x_io == x_size-1) and (y_io == y_size-1)) ) + + ### define type and name + + platform_type = 'tsar_mwmr' + platform_name = '%s_%d_%d_%d' % ( platform_type, x_size, y_size , nb_procs ) + + ### define physical segments replicated in all clusters + + ram_base = 0x0000000000 + ram_size = 0x1000000 # 16 Mbytes + + xcu_base = 0x00B0000000 + xcu_size = 0x1000 # 4 Kbytes + + mwr_base = 0x00B1000000 + mwr_size = 0x1000 # 4 Kbytes + + mmc_base = 0x00B2000000 + mmc_size = 0x1000 # 4 Kbytes + + ### define physical segments for external peripherals + ## These segments are only defined in cluster_io + + bdv_base = 0x00B3000000 + bdv_size = 0x1000 # 4kbytes + + tty_base = 0x00B4000000 + tty_size = 0x4000 # 16 Kbytes + + nic_base = 0x00B5000000 + nic_size = 0x80000 # 512 kbytes + + cma_base = 0x00B6000000 + cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics + + fbf_base = 0x00B7000000 + fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes + + pic_base = 0x00B8000000 + pic_size = 0x1000 # 4 Kbytes + + iob_base = 0x00BE000000 + iob_size = 0x1000 # 4 bytes + + rom_base = 0x00BFC00000 + rom_size = 0x4000 # 16 Kbytes + + ### define bootloader vsegs base addresses and sizes + ### We want to pack these 4 vsegs in the same big page + ### => boot cost is one BIG page in cluster[0][0] + + boot_mapping_vbase = 0x00000000 # ident + boot_mapping_size = 0x00080000 # 512 Kbytes + + boot_code_vbase = 0x00080000 # ident + boot_code_size = 0x00040000 # 256 Kbytes + + boot_data_vbase = 0x000C0000 # ident + boot_data_size = 0x000C0000 # 768 Kbytes + + boot_stack_vbase = 0x00180000 # ident + boot_stack_size = 0x00080000 # 512 Kbytes + + ### define kernel vsegs base addresses and sizes + ### code, init, ptab, heap & sched vsegs are replicated in all clusters. + ### data & uncdata vsegs are only mapped in cluster[0][0]. + + kernel_code_vbase = 0x80000000 + kernel_code_size = 0x00100000 # 1 Mbytes per cluster + + kernel_init_vbase = 0x80100000 + kernel_init_size = 0x00100000 # 1 Mbytes per cluster + + kernel_data_vbase = 0x90000000 + kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0,0] + + kernel_ptab_vbase = 0xE0000000 + kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster + + kernel_heap_vbase = 0xD0000000 + kernel_heap_size = 0x00200000 # 2 Mbytes per cluster + + kernel_sched_vbase = 0xA0000000 + kernel_sched_size = 0x00002000*nb_procs # 8 Kbytes per proc per cluster + + ######################### + ### create mapping + ######################### + + mapping = Mapping( name = platform_name, + x_size = x_size, + y_size = y_size, + nprocs = nb_procs, + x_width = x_width, + y_width = y_width, + p_width = p_width, + paddr_width = paddr_width, + coherence = True, + irq_per_proc = irq_per_proc, + use_ramdisk = use_ramdisk, + x_io = x_io, + y_io = y_io, + peri_increment = peri_increment, + ram_base = ram_base, + ram_size = ram_size ) + + + ############################# + ### Hardware Components + ############################# + + for x in xrange( x_size ): + for y in xrange( y_size ): + cluster_xy = (x << y_width) + y; + offset = cluster_xy << (paddr_width - x_width - y_width) + + ### components replicated in all clusters + ram = mapping.addRam( 'RAM', base = ram_base + offset, + size = ram_size ) + + mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, + size = mmc_size, ptype = 'MMC' ) + + mwr = mapping.addPeriph( 'MWR', base = mwr_base + offset, + size = mwr_size, ptype = 'MWR', subtype = 'GCD', + arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 ) + + xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, + size = xcu_size, ptype = 'XCU', + channels = nb_procs * irq_per_proc, + arg0 = 32, arg1 = 32, arg2 = 32, arg3 = 16 ) + + mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) + mapping.addIrq( xcu, index = 1, isrtype = 'ISR_MWR' , channel = 2 ) + + for p in xrange ( nb_procs ): + mapping.addProc( x, y, p ) + + ### external peripherals in cluster_io + if ( (x==x_io) and (y==y_io) ): + + iob = mapping.addPeriph( 'IOB', base = iob_base + offset, size = iob_size, + ptype = 'IOB' ) + + bdv = mapping.addPeriph( 'BDV', base = bdv_base + offset, size = bdv_size, + ptype = 'IOC', subtype = 'BDV' ) + + tty = mapping.addPeriph( 'TTY', base = tty_base + offset, size = tty_size, + ptype = 'TTY', channels = nb_ttys ) + + nic = mapping.addPeriph( 'NIC', base = nic_base + offset, size = nic_size, + ptype = 'NIC', channels = nb_nics ) + + cma = mapping.addPeriph( 'CMA', base = cma_base + offset, size = cma_size, + ptype = 'CMA', channels = nb_cmas ) + + fbf = mapping.addPeriph( 'FBF', base = fbf_base + offset, size = fbf_size, + ptype = 'FBF', arg0 = fbf_width, arg1 = fbf_width ) + + rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size, + ptype = 'ROM' ) + + pic = mapping.addPeriph( 'PIC', base = pic_base + offset, size = pic_size, + ptype = 'PIC', channels = 32 ) + + mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 ) + mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 ) + + mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 ) + mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 ) + + mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 ) + mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 ) + mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 ) + mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 ) + + mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 ) + + mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 ) + mapping.addIrq( pic, index = 17, isrtype = 'ISR_TTY_RX', channel = 1 ) + mapping.addIrq( pic, index = 18, isrtype = 'ISR_TTY_RX', channel = 2 ) + mapping.addIrq( pic, index = 19, isrtype = 'ISR_TTY_RX', channel = 3 ) + mapping.addIrq( pic, index = 20, isrtype = 'ISR_TTY_RX', channel = 4 ) + mapping.addIrq( pic, index = 21, isrtype = 'ISR_TTY_RX', channel = 5 ) + mapping.addIrq( pic, index = 22, isrtype = 'ISR_TTY_RX', channel = 6 ) + mapping.addIrq( pic, index = 23, isrtype = 'ISR_TTY_RX', channel = 7 ) + + + #################################### + ### Boot & Kernel vsegs mapping + #################################### + + ### global vsegs for boot_loader + ### we want to pack those 4 vsegs in the same big page + ### => same flags CXW_ / identity mapping / non local / big page + + mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, + 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', + identity = True , local = False, big = True ) + + mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, + 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True , local = False, big = True ) + + mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, + 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True , local = False, big = True ) + + mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, + 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True , local = False, big = True ) + + ### global vseg kernel_data : big / non local + ### Only mapped in cluster[0][0] + mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, + 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', + binpath = 'build/kernel/kernel.elf', + local = False, big = True ) + + ### global vsegs kernel_code, kernel_init : big / local + ### replicated in all clusters with the same name & same vbase + for x in xrange( x_size ): + for y in xrange( y_size ): + mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, + 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', + binpath = 'build/kernel/kernel.elf', + local = True, big = True ) + + mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, + 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', + binpath = 'build/kernel/kernel.elf', + local = True, big = True ) + + ### Global vsegs kernel_ptab_x_y : big / non local + ### one vseg per cluster: name indexed by (x,y) + for x in xrange( x_size ): + for y in xrange( y_size ): + offset = ((x << y_width) + y) * kernel_ptab_size + base = kernel_ptab_vbase + offset + mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), base, kernel_ptab_size, + 'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM', + local = False , big = True ) + + ### global vsegs kernel_sched_x_y : small / non local + ### one vseg per cluster with name indexed by (x,y) + for x in xrange( x_size ): + for y in xrange( y_size ): + offset = ((x << y_width) + y) * kernel_sched_size + mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y), + kernel_sched_vbase + offset , kernel_sched_size, + 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM', + local = False, big = False ) + + ### global vsegs kernel_heap_x_y : big / non local + ### one vseg per cluster with name indexed by (x,y) + for x in xrange( x_size ): + for y in xrange( y_size ): + offset = ((x << y_width) + y) * kernel_heap_size + mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y), + kernel_heap_vbase + offset , kernel_heap_size, + 'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM', + local = False, big = True ) + + ### global vsegs for external peripherals : non local / big page + mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', + local = False, big = True ) + + mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', + local = False, big = True ) + + mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', + local = False, big = True ) + + mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', + local = False, big = True ) + + mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', + local = False, big = True ) + + mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', + local = False, big = True ) + + mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', + local = False, big = True ) + + mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', + vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', + local = False, big = True ) + + ### global vsegs for internal peripherals : non local / small pages + ### allocated in all clusters with name indexed by (x,y) + ### as vbase address is incremented by (cluster_xy * vseg_increment) + for x in xrange( x_size ): + for y in xrange( y_size ): + offset = ((x << y_width) + y) * peri_increment + + mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU', + local = False, big = False ) + + mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR', + local = False, big = False ) + + mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC', + local = False, big = False ) + + return mapping + +################################# platform test #################################### + +if __name__ == '__main__': + + mapping = arch( x_size = 2, + y_size = 2, + nb_procs = 2 ) + +# print mapping.netbsd_dts() + + print mapping.xml() + +# print mapping.giet_vsegs() + + +# Local Variables: +# tab-width: 4; +# c-basic-offset: 4; +# c-file-offsets:((innamespace . 0)(inline-open . 0)); +# indent-tabs-mode: nil; +# End: +# +# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /trunk/platforms/tsar_generic_mwmr/hard_config.h =================================================================== --- /trunk/platforms/tsar_generic_mwmr/hard_config.h (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/hard_config.h (revision 956) @@ -0,0 +1,113 @@ +/* Generated by genmap for tsar_iob_2_2_4_transpose */ + +#ifndef HARD_CONFIG_H +#define HARD_CONFIG_H + +/* General platform parameters */ + +#define X_SIZE 2 +#define Y_SIZE 2 +#define X_WIDTH 4 +#define Y_WIDTH 4 +#define P_WIDTH 4 +#define X_IO 0 +#define Y_IO 0 +#define NB_PROCS_MAX 4 +#define IRQ_PER_PROCESSOR 4 +#define RESET_ADDRESS 0xbfc00000 +#define NB_TOTAL_PROCS 16 + +/* Peripherals */ + +#define NB_TTY_CHANNELS 1 +#define NB_IOC_CHANNELS 1 +#define NB_NIC_CHANNELS 1 +#define NB_CMA_CHANNELS 2 +#define NB_TIM_CHANNELS 0 +#define NB_DMA_CHANNELS 4 + +#define USE_XCU 1 +#define USE_IOB 1 +#define USE_PIC 1 +#define USE_FBF 1 + +#define USE_IOC_BDV 1 +#define USE_IOC_SPI 0 +#define USE_IOC_HBA 0 +#define USE_IOC_RDK 0 + +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 + +#define XCU_NB_INPUTS 32 + +/* base addresses and sizes for physical segments */ + +#define SEG_RAM_BASE 0x0 +#define SEG_RAM_SIZE 0x1000000 + +#define SEG_CMA_BASE 0xb6000000 +#define SEG_CMA_SIZE 0x2000 + +#define SEG_DMA_BASE 0xb1000000 +#define SEG_DMA_SIZE 0x1000 + +#define SEG_FBF_BASE 0xb7000000 +#define SEG_FBF_SIZE 0x4000 + +#define SEG_IOB_BASE 0xbe000000 +#define SEG_IOB_SIZE 0x1000 + +#define SEG_IOC_BASE 0xb3000000 +#define SEG_IOC_SIZE 0x1000 + +#define SEG_MMC_BASE 0xb2000000 +#define SEG_MMC_SIZE 0x1000 + +#define SEG_MWR_BASE 0xffffffff +#define SEG_MWR_SIZE 0x0 + +#define SEG_ROM_BASE 0xbfc00000 +#define SEG_ROM_SIZE 0x4000 + +#define SEG_SIM_BASE 0xffffffff +#define SEG_SIM_SIZE 0x0 + +#define SEG_NIC_BASE 0xb5000000 +#define SEG_NIC_SIZE 0x80000 + +#define SEG_PIC_BASE 0xb8000000 +#define SEG_PIC_SIZE 0x1000 + +#define SEG_TIM_BASE 0xffffffff +#define SEG_TIM_SIZE 0x0 + +#define SEG_TTY_BASE 0xb4000000 +#define SEG_TTY_SIZE 0x4000 + +#define SEG_XCU_BASE 0xb0000000 +#define SEG_XCU_SIZE 0x1000 + +#define SEG_RDK_BASE 0xffffffff +#define SEG_RDK_SIZE 0x0 + +#define SEG_DROM_BASE 0xffffffff +#define SEG_DROM_SIZE 0x0 + +#define PERI_CLUSTER_INCREMENT 0x10000 + +/* physical base addresses for identity mapped vsegs */ +/* used by the GietVM OS */ + +#define SEG_BOOT_MAPPING_BASE 0x0 +#define SEG_BOOT_MAPPING_SIZE 0x80000 + +#define SEG_BOOT_CODE_BASE 0x80000 +#define SEG_BOOT_CODE_SIZE 0x40000 + +#define SEG_BOOT_DATA_BASE 0xc0000 +#define SEG_BOOT_DATA_SIZE 0xc0000 + +#define SEG_BOOT_STACK_BASE 0x180000 +#define SEG_BOOT_STACK_SIZE 0x80000 +#endif Index: /trunk/platforms/tsar_generic_mwmr/top.cpp =================================================================== --- /trunk/platforms/tsar_generic_mwmr/top.cpp (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/top.cpp (revision 956) @@ -0,0 +1,1589 @@ +/////////////////////////////////////////////////////////////////////////////// +// File: top.cpp (for tsar_generic_mwmr platform) +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : february 2015 +// This program is released under the GNU public license +/////////////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture with an external IO network +// emulating a PCI or Hypertransport I/O bus to access 7 external peripherals: +// +// - BROM : boot ROM +// - FBUF : Frame Buffer +// - MTTY : multi TTY (one channel) +// - MNIC : Network controller (up to 2 channels) +// - CDMA : Chained Buffer DMA controller (up to 4 channels) +// - BDEV : Dlock Device controler (one channel) +// - IOPI : HWI to SWI translator. +// +// This I/0 bus is connected to internal address space through two IOB bridges +// located in cluster[0][0] and cluster[X_SIZE-1][Åž_SIZE-1]. +// +// The internal physical address space is 40 bits, and the cluster index +// is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, +// Y is encoded on 4 bits, whatever the actual mesh size. +// => at most 16 * 16 clusters. Each cluster contains up to 4 processors. +// +// It contains 3 networks: +// +// 1) the "INT" network supports Read/Write transactions +// between processors and L2 caches or peripherals. +// (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) +// It supports also coherence transactions between L1 & L2 caches. +// 3) the "RAM" network emulates the 3D network between L2 caches +// and L3 caches, and is implemented as a 2D mesh between the L2 caches, +// the two IO bridges and the physical RAMs disributed in all clusters. +// (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) +// 4) the IOX network connects the two IO bridge components to the +// 7 external peripheral controllers. +// (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) +// +// The external peripherals HWI IRQs are translated to WTI IRQs by the +// external IOPIC component, that must be configured by the OS to route +// these WTI IRQS to one or several internal XICU components. +// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] +// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] +// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] +// - IOPIC HWI[8] connected to IRQ_BDEV +// - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] +// +// Besides the external peripherals, each cluster contains one XICU component, +// and one MWMR coprocessor. +// The XICU component is mainly used to handle WTI IRQs, as only the MMC HWI IRQ +// is connected to XICU in each cluster. +// +// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) +// contain an extra IO bridge component. These IOB0 & IOB1 components are +// connected to the three networks (INT, RAM, IOX). +// +// - It uses two dspin_local_crossbar per cluster to implement the +// local interconnect correponding to the INT network. +// - It uses three dspin_local_crossbar per cluster to implement the +// local interconnect correponding to the coherence INT network. +// - It uses two virtual_dspin_router per cluster to implement +// the INT network (routing both the direct and coherence trafic). +// - It uses two dspin_router per cluster to implement the RAM network. +// - It uses the vci_cc_vcache_wrapper. +// - It uses the vci_mem_cache. +// - It contains one vci_xicu and one vci_multi_mwmr per cluster. +// - It contains one vci_simple ram per cluster to model the L3 cache. +// +// The TsarIobCluster component is defined in files +// tsar_iob_cluster.* (with * = cpp, h, sd) +// +// The main hardware parameters must be defined in the hard_config.h file : +// - X_SIZE : number of clusters in a row +// - Y_SIZE : number of clusters in a column +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_TTY_CHANNELS : number of TTY channels in I/O network (up to 16) +// - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) +// - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs +// +// Some secondary hardware parameters must be defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - BDEV_IMAGE_NAME : file pathname for block device +// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// |X_ID|Y_ID| LADR | OFFSET | +// | 4 | 4 | 8 | 24 | +// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// |X_ID|Y_ID| L_ID | +// | 4 | 4 | 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" + +#include "tsar_mwmr_cluster.h" +#include "vci_chbuf_dma.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_simple_rom.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_iox_network.h" +#include "vci_iox_network.h" +#include "vci_iopic.h" + +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// OS +/////////////////////////////////////////////////// +#define USE_ALMOS 0 + +#define almos_bootloader_pathname "bootloader.bin" +#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" +#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// + +#define USING_OPENMP 0 + +#if USING_OPENMP +#include +#endif + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_int_cmd_width 39 +#define dspin_int_rsp_width 32 + +#define dspin_ram_cmd_width 64 +#define dspin_ram_rsp_width 64 + +/////////////////////////////////////////////////////////// +// VCI fields width for the 3 VCI networks +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 + +#define vci_plen_width 8 +#define vci_address_width 40 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#include "hard_config.h" + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#define XMAX X_SIZE +#define YMAX Y_SIZE + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" + +#define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +#define cluster(x,y) ((y) + ((x) << 4)) + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// + +#define MAX_FROZEN_CYCLES 1000000 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// + +// All physical segments base addresses and sizes are defined +// in the hard_config.h file. For replicated segments, the +// base address is incremented by a cluster offset: +// offset = cluster(x,y) << (address_width-x_width-y_width); + +//////////////////////////////////////////////////////////////////////// +// SRCID definition +//////////////////////////////////////////////////////////////////////// +// All initiators are in the same indexing space (14 bits). +// The SRCID is structured in two fields: +// - The 8 MSB bits define the cluster index (left aligned) +// - The 6 LSB bits define the local index. +// Two different initiators cannot have the same SRCID, but a given +// initiator can have two alias SRCIDs: +// - Internal initiators (procs, mwmr) are replicated in all clusters, +// and each initiator has one single SRCID. +// - External initiators (bdev, cdma) are not replicated, but can be +// accessed in 2 clusters : cluster_iob0 and cluster_iob1. +// They have the same local index, but two different cluster indexes. +// +// As cluster_iob0 and cluster_iob1 contain both internal initiators +// and external initiators, they must have different local indexes. +// Consequence: For a local interconnect, the INI_ID port index +// is NOT equal to the SRCID local index, and the local interconnect +// must make a translation: SRCID => INI_ID +//////////////////////////////////////////////////////////////////////// + +#define PROC_LOCAL_SRCID 0x0 // from 0 to 7 +#define MWMR_LOCAL_SRCID 0x8 +#define IOBX_LOCAL_SRCID 0x9 +#define MEMC_LOCAL_SRCID 0xA +#define CDMA_LOCAL_SRCID 0xB +#define BDEV_LOCAL_SRCID 0xC +#define IOPI_LOCAL_SRCID 0xD + +/////////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for INT local interconnect +/////////////////////////////////////////////////////////////////////// + +#define INT_MEMC_TGT_ID 0 +#define INT_XICU_TGT_ID 1 +#define INT_MWMR_TGT_ID 2 +#define INT_IOBX_TGT_ID 3 + +#define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) +#define INT_MWMR_INI_ID (NB_PROCS_MAX) +#define INT_IOBX_INI_ID (NB_PROCS_MAX+1) + +/////////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for RAM local interconnect +/////////////////////////////////////////////////////////////////////// + +#define RAM_XRAM_TGT_ID 0 + +#define RAM_MEMC_INI_ID 0 +#define RAM_IOBX_INI_ID 1 + +/////////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for I0X local interconnect +/////////////////////////////////////////////////////////////////////// + +#define IOX_FBUF_TGT_ID 0 +#define IOX_BDEV_TGT_ID 1 +#define IOX_MNIC_TGT_ID 2 +#define IOX_CDMA_TGT_ID 3 +#define IOX_BROM_TGT_ID 4 +#define IOX_MTTY_TGT_ID 5 +#define IOX_IOPI_TGT_ID 6 +#define IOX_IOB0_TGT_ID 7 +#define IOX_IOB1_TGT_ID 8 + +#define IOX_BDEV_INI_ID 0 +#define IOX_CDMA_INI_ID 1 +#define IOX_IOPI_INI_ID 2 +#define IOX_IOB0_INI_ID 3 +#define IOX_IOB1_INI_ID 4 + +//////////////////////////////////////////////////////////////////////// +int _main(int argc, char *argv[]) +//////////////////////////////////////////////////////////////////////// +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + + char soft_name[256] = ROM_SOFT_NAME; // pathname: binary code + size_t ncycles = 4000000000; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc + size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc + size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram + bool debug_iob = false; // trace iob0 & iob1 when true + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 + size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 + size_t x_width = X_WIDTH; // # of bits for x + size_t y_width = Y_WIDTH; // # of bits for y + size_t p_width = P_WIDTH; // # of bits for lpid + +#if USING_OPENMP + size_t simul_period = 1000000; +#else + size_t simul_period = 1; +#endif + + assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and + "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); + + assert( P_WIDTH <= 4 and + "ERROR: we must have P_WIDTH <= 4"); + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1> 4; + size_t y = debug_memc_id & 0xF; + if( (x>=XMAX) || (y>=YMAX) ) + { + std::cout << "MEMCID parameter does'nt fit XMAX/YMAX" << std::endl; + std::cout << " - MEMCID = " << std::hex << debug_memc_id << std::endl; + std::cout << " - XMAX = " << std::hex << XMAX << std::endl; + std::cout << " - YMAX = " << std::hex << YMAX << std::endl; + exit(0); + } + } + else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1> 4; + size_t y = debug_xram_id & 0xF; + if( (x>=XMAX) || (y>=YMAX) ) + { + std::cout << "XRAMID parameter does'nt fit XMAX/YMAX" << std::endl; + exit(0); + } + } + else if ((strcmp(argv[n],"-IOB") == 0) && (n+1> P_WIDTH ; + size_t x = cluster_xy >> 4; + size_t y = cluster_xy & 0xF; + if( (x>=XMAX) || (y>=YMAX) ) + { + std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; + std::cout << " - PROCID = " << std::hex << debug_proc_id << std::endl; + std::cout << " - XMAX = " << std::hex << XMAX << std::endl; + std::cout << " - YMAX = " << std::hex << YMAX << std::endl; + exit(0); + } + } + else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) + { + threads_nr = atoi(argv[n+1]); + threads_nr = (threads_nr < 1) ? 1 : threads_nr; + } + else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) + { + frozen_cycles = atoi(argv[n+1]); + } + else + { + std::cout << " Arguments are (key,value) couples." << std::endl; + std::cout << " The order is not important." << std::endl; + std::cout << " Accepted arguments are :" << std::endl << std::endl; + std::cout << " - ROM pathname_for_embedded_soft" << std::endl; + std::cout << " - DISK pathname_for_disk_image" << std::endl; + std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl; + std::cout << " - DEBUG debug_start_cycle" << std::endl; + std::cout << " - THREADS simulator's threads number" << std::endl; + std::cout << " - FROZEN max_number_of_lines" << std::endl; + std::cout << " - MEMCID index_memc_to_be_traced" << std::endl; + std::cout << " - XRAMID index_xram_to_be_traced" << std::endl; + std::cout << " - PROCID index_proc_to_be_traced" << std::endl; + std::cout << " - IOB non_zero_value" << std::endl; + exit(0); + } + } + } + + // checking hardware parameters + assert( (XMAX <= 16) and + "The XMAX parameter cannot be larger than 16" ); + + assert( (YMAX <= 16) and + "The YMAX parameter cannot be larger than 16" ); + + assert( (NB_PROCS_MAX <= (1 << P_WIDTH)) and + "NB_PROCS_MAX parameter cannot be larger than 2^P_WIDTH" ); + + assert( (NB_DMA_CHANNELS <= 8) and + "The NB_DMA_CHANNELS parameter cannot be larger than 8" ); + + assert( (NB_TTY_CHANNELS >= 1) and (NB_TTY_CHANNELS <= 16) and + "The NB_TTY_CHANNELS parameter cannot be larger than 16" ); + + assert( (NB_NIC_CHANNELS <= 2) and + "The NB_NIC_CHANNELS parameter cannot be larger than 2" ); + + assert( (NB_CMA_CHANNELS <= 4) and + "The NB_CMA_CHANNELS parameter cannot be larger than 4" ); + + std::cout << std::endl << std::dec + << " - XMAX = " << XMAX << std::endl + << " - YMAX = " << YMAX << std::endl + << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl + << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl + << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl + << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl + << " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl + << " - MEMC_WAYS = " << MEMC_WAYS << std::endl + << " - MEMC_SETS = " << MEMC_SETS << std::endl + << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl + << " - MAX_FROZEN = " << frozen_cycles << std::endl + << " - NCYCLES = " << ncycles << std::endl + << " - DEBUG_PROCID = " << debug_proc_id << std::endl + << " - DEBUG_MEMCID = " << debug_memc_id << std::endl + << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; + + std::cout << std::endl; + +#if USING_OPENMP + omp_set_dynamic(false); + omp_set_num_threads(threads_nr); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + + // Define VciParams objects + typedef soclib::caba::VciParams vci_param_int; + + typedef soclib::caba::VciParams vci_param_ext; + + ///////////////////////////////////////////////////////////////////// + // INT network mapping table + // - two levels address decoding for commands + // - two levels srcid decoding for responses + // - NB_PROCS_MAX + 2 (MWMR, IOBX) local initiators per cluster + // - 4 local targets (MEMC, XICU, MWMR, IOBX) per cluster + ///////////////////////////////////////////////////////////////////// + MappingTable maptab_int( vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FF000000); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX; y++) + { + uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + bool config = true; + bool cacheable = true; + + // the four following segments are defined in all clusters + + std::ostringstream smemc_conf; + smemc_conf << "int_seg_memc_conf_" << x << "_" << y; + maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, + IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); + + std::ostringstream smemc_xram; + smemc_xram << "int_seg_memc_xram_" << x << "_" << y; + maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, + IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); + + std::ostringstream sxicu; + sxicu << "int_seg_xicu_" << x << "_" << y; + maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, + IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); + + std::ostringstream smwmr; + smwmr << "int_seg_mwmr_" << x << "_" << y; + maptab_int.add(Segment(smwmr.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, + IntTab(cluster(x,y), INT_MWMR_TGT_ID), not cacheable)); + + // the following segments are only defined in cluster_iob0 or in cluster_iob1 + + if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) + { + std::ostringstream siobx; + siobx << "int_seg_iobx_" << x << "_" << y; + maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); + + std::ostringstream stty; + stty << "int_seg_mtty_" << x << "_" << y; + maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream sfbf; + sfbf << "int_seg_fbuf_" << x << "_" << y; + maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream sbdv; + sbdv << "int_seg_bdev_" << x << "_" << y; + maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream snic; + snic << "int_seg_mnic_" << x << "_" << y; + maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream srom; + srom << "int_seg_brom_" << x << "_" << y; + maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); + + std::ostringstream scma; + scma << "int_seg_cdma_" << x << "_" << y; + maptab_int.add(Segment(scma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream spic; + spic << "int_seg_iopi_" << x << "_" << y; + maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + } + + // This define the mapping between the SRCIDs + // and the port index on the local interconnect. + + maptab_int.srcid_map( IntTab( cluster(x,y), MWMR_LOCAL_SRCID ), + IntTab( cluster(x,y), INT_MWMR_INI_ID ) ); + + maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), + IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); + + maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), + IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); + + for ( size_t p = 0 ; p < NB_PROCS_MAX; p++ ) + maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), + IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); + } + } + std::cout << "INT network " << maptab_int << std::endl; + + ///////////////////////////////////////////////////////////////////////// + // RAM network mapping table + // - two levels address decoding for commands + // - two levels srcid decoding for responses + // - 2 local initiators (MEMC, IOBX) per cluster + // (IOBX component only in cluster_iob0 and cluster_iob1) + // - 1 local target (XRAM) per cluster + //////////////////////////////////////////////////////////////////////// + MappingTable maptab_ram( vci_address_width, + IntTab(x_width+y_width, 0), + IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), + 0x00FF000000); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + + std::ostringstream sxram; + sxram << "ext_seg_xram_" << x << "_" << y; + maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, + SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); + } + } + + // This define the mapping between the initiators SRCID + // and the port index on the RAM local interconnect. + // External initiator have two alias SRCID (iob0 / iob1) + + maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); + + std::cout << "RAM network " << maptab_ram << std::endl; + + /////////////////////////////////////////////////////////////////////// + // IOX network mapping table + // - two levels address decoding for commands (9, 7) bits + // - two levels srcid decoding for responses + // - 5 initiators (IOB0, IOB1, BDEV, CDMA, IOPI) + // - 9 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) + // + // Address bit 32 is used to determine if a command must be routed to + // IOB0 or IOB1. + /////////////////////////////////////////////////////////////////////// + MappingTable maptab_iox( + vci_address_width, + IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), + IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), + 0x00FF000000); + + // External peripherals segments + // When there is more than one cluster, external peripherals can be accessed + // through two segments, depending on the used IOB (IOB0 or IOB1). + + const uint64_t iob0_base = ((uint64_t)cluster_iob0) + << (vci_address_width - x_width - y_width); + + maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, + IntTab(0, IOX_MTTY_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, + IntTab(0, IOX_FBUF_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_bdev_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, + IntTab(0, IOX_BDEV_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, + IntTab(0, IOX_MNIC_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, + IntTab(0, IOX_CDMA_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, + IntTab(0, IOX_BROM_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, + IntTab(0, IOX_IOPI_TGT_ID), false)); + + if ( cluster_iob0 != cluster_iob1 ) + { + const uint64_t iob1_base = ((uint64_t)cluster_iob1) + << (vci_address_width - x_width - y_width); + + maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, + IntTab(0, IOX_MTTY_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, + IntTab(0, IOX_FBUF_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_bdev_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, + IntTab(0, IOX_BDEV_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, + IntTab(0, IOX_MNIC_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, + IntTab(0, IOX_CDMA_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, + IntTab(0, IOX_BROM_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, + IntTab(0, IOX_IOPI_TGT_ID), false)); + } + + // If there is more than one cluster, external peripherals + // can access RAM through two segments (IOB0 / IOB1). + // As IOMMU is not activated, addresses are 40 bits (physical addresses), + // and the choice depends on address bit A[32]. + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + const bool wti = true; + const bool cacheable = true; + + const uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + + const uint64_t xicu_base = SEG_XCU_BASE + offset; + + if ( (y & 0x1) == 0 ) // use IOB0 + { + std::ostringstream sxcu0; + sxcu0 << "iox_seg_xcu0_" << x << "_" << y; + maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, + IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); + + std::ostringstream siob0; + siob0 << "iox_seg_ram0_" << x << "_" << y; + maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, + IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); + } + else // USE IOB1 + { + std::ostringstream sxcu1; + sxcu1 << "iox_seg_xcu1_" << x << "_" << y; + maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, + IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); + + std::ostringstream siob1; + siob1 << "iox_seg_ram1_" << x << "_" << y; + maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, + IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); + } + } + } + + // This define the mapping between the external initiators (SRCID) + // and the port index on the IOX local interconnect. + + maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , + IntTab( 0, IOX_CDMA_INI_ID ) ); + maptab_iox.srcid_map( IntTab( 0, BDEV_LOCAL_SRCID ) , + IntTab( 0, IOX_BDEV_INI_ID ) ); + maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , + IntTab( 0, IOX_IOPI_INI_ID ) ); + maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , + IntTab( 0, IOX_IOB0_INI_ID ) ); + + if ( cluster_iob0 != cluster_iob1 ) + { + maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , + IntTab( 0, IOX_IOB1_INI_ID ) ); + } + + std::cout << "IOX network " << maptab_iox << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + sc_signal signal_irq_false; + sc_signal signal_irq_bdev; + sc_signal signal_irq_mtty_rx[NB_TTY_CHANNELS]; + sc_signal signal_irq_mnic_rx[NB_NIC_CHANNELS]; + sc_signal signal_irq_mnic_tx[NB_NIC_CHANNELS]; + sc_signal signal_irq_cdma[NB_CMA_CHANNELS]; + + // VCI signals for IOX network + VciSignals signal_vci_ini_iob0("signal_vci_ini_iob0"); + VciSignals signal_vci_ini_iob1("signal_vci_ini_iob1"); + VciSignals signal_vci_ini_bdev("signal_vci_ini_bdev"); + VciSignals signal_vci_ini_cdma("signal_vci_ini_cdma"); + VciSignals signal_vci_ini_iopi("signal_vci_ini_iopi"); + + VciSignals signal_vci_tgt_iob0("signal_vci_tgt_iob0"); + VciSignals signal_vci_tgt_iob1("signal_vci_tgt_iob1"); + VciSignals signal_vci_tgt_mtty("signal_vci_tgt_mtty"); + VciSignals signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); + VciSignals signal_vci_tgt_mnic("signal_vci_tgt_mnic"); + VciSignals signal_vci_tgt_brom("signal_vci_tgt_brom"); + VciSignals signal_vci_tgt_bdev("signal_vci_tgt_bdev"); + VciSignals signal_vci_tgt_cdma("signal_vci_tgt_cdma"); + VciSignals signal_vci_tgt_iopi("signal_vci_tgt_iopi"); + + // Horizontal inter-clusters INT network DSPIN + DspinSignals*** signal_dspin_int_cmd_h_inc = + alloc_elems >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); + DspinSignals*** signal_dspin_int_cmd_h_dec = + alloc_elems >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); + DspinSignals*** signal_dspin_int_rsp_h_inc = + alloc_elems >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); + DspinSignals*** signal_dspin_int_rsp_h_dec = + alloc_elems >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); + + // Vertical inter-clusters INT network DSPIN + DspinSignals*** signal_dspin_int_cmd_v_inc = + alloc_elems >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); + DspinSignals*** signal_dspin_int_cmd_v_dec = + alloc_elems >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); + DspinSignals*** signal_dspin_int_rsp_v_inc = + alloc_elems >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); + DspinSignals*** signal_dspin_int_rsp_v_dec = + alloc_elems >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); + + // Mesh boundaries INT network DSPIN + DspinSignals**** signal_dspin_false_int_cmd_in = + alloc_elems >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); + DspinSignals**** signal_dspin_false_int_cmd_out = + alloc_elems >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); + DspinSignals**** signal_dspin_false_int_rsp_in = + alloc_elems >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); + DspinSignals**** signal_dspin_false_int_rsp_out = + alloc_elems >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); + + + // Horizontal inter-clusters RAM network DSPIN + DspinSignals** signal_dspin_ram_cmd_h_inc = + alloc_elems >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_cmd_h_dec = + alloc_elems >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_rsp_h_inc = + alloc_elems >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_rsp_h_dec = + alloc_elems >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); + + // Vertical inter-clusters RAM network DSPIN + DspinSignals** signal_dspin_ram_cmd_v_inc = + alloc_elems >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_cmd_v_dec = + alloc_elems >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_rsp_v_inc = + alloc_elems >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_rsp_v_dec = + alloc_elems >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); + + // Mesh boundaries RAM network DSPIN + DspinSignals*** signal_dspin_false_ram_cmd_in = + alloc_elems >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_cmd_out = + alloc_elems >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_rsp_in = + alloc_elems >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_rsp_out = + alloc_elems >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); + + //////////////////////////// + // Loader + //////////////////////////// + +#if USE_ALMOS + soclib::common::Loader loader(almos_bootloader_pathname, + almos_archinfo_pathname, + almos_kernel_pathname); +#else + soclib::common::Loader loader(soft_name); +#endif + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////////////////// + // Instanciated Hardware Components + //////////////////////////////////////// + + std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; + + const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; + const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8; + + // IOX network + VciIoxNetwork* iox_network; + iox_network = new VciIoxNetwork( "iox_network", + maptab_iox, + nb_iox_targets, + nb_iox_initiators ); + // boot ROM + VciSimpleRom* brom; + brom = new VciSimpleRom( "brom", + IntTab(0, IOX_BROM_TGT_ID), + maptab_iox, + loader ); + // Network Controller + VciMultiNic* mnic; + mnic = new VciMultiNic( "mnic", + IntTab(0, IOX_MNIC_TGT_ID), + maptab_iox, + NB_NIC_CHANNELS, + 0, // mac_4 address + 0, // mac_2 address + 1 ); // NIC_MODE_SYNTHESIS + + // Frame Buffer + VciFrameBuffer* fbuf; + fbuf = new VciFrameBuffer( "fbuf", + IntTab(0, IOX_FBUF_TGT_ID), + maptab_iox, + FBUF_X_SIZE, FBUF_Y_SIZE ); + + // Block Device + // for AHCI + // std::vector filenames; + // filenames.push_back(disk_name); // one single disk + VciBlockDeviceTsar* bdev; + bdev = new VciBlockDeviceTsar( "bdev", + maptab_iox, + IntTab(0, BDEV_LOCAL_SRCID), + IntTab(0, IOX_BDEV_TGT_ID), + disk_name, + 512, // block size + 64, // burst size (bytes) + 0 ); // disk latency + + // Chained Buffer DMA controller + VciChbufDma* cdma; + cdma = new VciChbufDma( "cdma", + maptab_iox, + IntTab(0, CDMA_LOCAL_SRCID), + IntTab(0, IOX_CDMA_TGT_ID), + 64, // burst size (bytes) + NB_CMA_CHANNELS ); + // Multi-TTY controller + std::vector vect_names; + for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) + { + std::ostringstream term_name; + term_name << "term" << tid; + vect_names.push_back(term_name.str().c_str()); + } + VciMultiTty* mtty; + mtty = new VciMultiTty( "mtty", + IntTab(0, IOX_MTTY_TGT_ID), + maptab_iox, + vect_names); + + // IOPIC + VciIopic* iopi; + iopi = new VciIopic( "iopi", + maptab_iox, + IntTab(0, IOPI_LOCAL_SRCID), + IntTab(0, IOX_IOPI_TGT_ID), + 32 ); // number of input HWI + // Clusters + TsarMwmrCluster* clusters[XMAX][YMAX]; + +#if USING_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for(size_t i = 0; i < (XMAX * YMAX); i++) + { + size_t x = i / YMAX; + size_t y = i % YMAX; + +#if USING_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; + std::cout << std::endl; + + const bool is_iob0 = (cluster(x,y) == cluster_iob0); + const bool is_iob1 = (cluster(x,y) == cluster_iob1); + const bool is_io_cluster = is_iob0 || is_iob1; + + const int iox_iob_ini_id = is_iob0 ? + IOX_IOB0_INI_ID : + IOX_IOB1_INI_ID ; + const int iox_iob_tgt_id = is_iob0 ? + IOX_IOB0_TGT_ID : + IOX_IOB1_TGT_ID ; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarMwmrCluster + ( + sc.str().c_str(), + NB_PROCS_MAX, + x, + y, + XMAX, + YMAX, + + maptab_int, + maptab_ram, + maptab_iox, + + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + p_width, + + INT_MEMC_TGT_ID, + INT_XICU_TGT_ID, + INT_MWMR_TGT_ID, + INT_IOBX_TGT_ID, + + INT_PROC_INI_ID, + INT_MWMR_INI_ID, + INT_IOBX_INI_ID, + + RAM_XRAM_TGT_ID, + + RAM_MEMC_INI_ID, + RAM_IOBX_INI_ID, + + is_io_cluster, + iox_iob_tgt_id, + iox_iob_ini_id, + + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + XCU_NB_INPUTS, + + loader, + + frozen_cycles, + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id), + debug_ok and debug_iob + ); + +#if USING_OPENMP + } // end critical +#endif + } // end for +#if USING_OPENMP + } +#endif + + std::cout << std::endl; + + /////////////////////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////////////////////// + + // IOX network connexion + iox_network->p_clk (signal_clk); + iox_network->p_resetn (signal_resetn); + iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); + iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); + iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); + iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); + + iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); + iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); + iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); + iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); + iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); + iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); + iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); + iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); + + if (cluster_iob0 != cluster_iob1) + { + iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); + iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); + } + + // BDEV connexion + bdev->p_clk (signal_clk); + bdev->p_resetn (signal_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF connexion + fbuf->p_clk (signal_clk); + fbuf->p_resetn (signal_resetn); + fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // MNIC connexion + mnic->p_clk (signal_clk); + mnic->p_resetn (signal_resetn); + mnic->p_vci (signal_vci_tgt_mnic); + for ( size_t i=0 ; ip_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + std::cout << " - MNIC connected" << std::endl; + + // BROM connexion + brom->p_clk (signal_clk); + brom->p_resetn (signal_resetn); + brom->p_vci (signal_vci_tgt_brom); + + std::cout << " - BROM connected" << std::endl; + + // MTTY connexion + mtty->p_clk (signal_clk); + mtty->p_resetn (signal_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + for ( size_t i=0 ; ip_irq[i] (signal_irq_mtty_rx[i]); + } + std::cout << " - MTTY connected" << std::endl; + + // CDMA connexion + cdma->p_clk (signal_clk); + cdma->p_resetn (signal_resetn); + cdma->p_vci_target (signal_vci_tgt_cdma); + cdma->p_vci_initiator (signal_vci_ini_cdma); + for ( size_t i=0 ; i<(NB_CMA_CHANNELS) ; i++) + { + cdma->p_irq[i] (signal_irq_cdma[i]); + } + + std::cout << " - CDMA connected" << std::endl; + + // IOPI connexion + iopi->p_clk (signal_clk); + iopi->p_resetn (signal_resetn); + iopi->p_vci_target (signal_vci_tgt_iopi); + iopi->p_vci_initiator (signal_vci_ini_iopi); + for ( size_t i=0 ; i<32 ; i++) + { + if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); + else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); + else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); + else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); + else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); + else if(i < 8) iopi->p_hwi[i] (signal_irq_false); + else if(i < 9) iopi->p_hwi[i] (signal_irq_bdev); + else if(i < 16) iopi->p_hwi[i] (signal_irq_false); + else if(i < 16+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); + else iopi->p_hwi[i] (signal_irq_false); + } + + std::cout << " - IOPIC connected" << std::endl; + + + // IOB0 cluster connexion to IOX network + (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); + (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); + + // IOB1 cluster connexion to IOX network + // (only when there is more than 1 cluster) + if ( cluster_iob0 != cluster_iob1 ) + { + (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); + (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); + } + + // All clusters Clock & RESET connexions + for ( size_t x = 0; x < (XMAX); x++ ) + { + for (size_t y = 0; y < YMAX; y++) + { + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (XMAX > 1) + { + for (size_t x = 0; x < (XMAX-1); x++) + { + for (size_t y = 0; y < YMAX; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); + clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); + clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); + clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); + clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); + clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); + } + + clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); + clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); + clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); + clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); + clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); + clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); + clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); + } + } + } + + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (YMAX > 1) + { + for (size_t y = 0; y < (YMAX-1); y++) + { + for (size_t x = 0; x < XMAX; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); + clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); + clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); + clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); + clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); + clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); + } + + clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); + clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); + clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); + clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); + clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); + clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); + clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); + } + } + } + + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < YMAX; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); + clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); + clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); + clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); + clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); + clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); + clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); + } + + clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); + clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); + + clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); + } + + std::cout << "East & West boundaries established" << std::endl; + + // North & South boundary clusters connections + for (size_t x = 0; x < XMAX; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); + clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); + clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); + clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); + clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); + clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); + clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); + } + + clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); + + clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); + } + + std::cout << "North & South boundaries established" << std::endl << std::endl; + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + + signal_resetn = false; + signal_irq_false = false; + + // network boundaries signals + for (size_t x = 0; x < XMAX ; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + for (size_t a = 0; a < 4; a++) + { + for (size_t k = 0; k < 3; k++) + { + signal_dspin_false_int_cmd_in[x][y][a][k].write = false; + signal_dspin_false_int_cmd_in[x][y][a][k].read = true; + signal_dspin_false_int_cmd_out[x][y][a][k].write = false; + signal_dspin_false_int_cmd_out[x][y][a][k].read = true; + } + + for (size_t k = 0; k < 2; k++) + { + signal_dspin_false_int_rsp_in[x][y][a][k].write = false; + signal_dspin_false_int_rsp_in[x][y][a][k].read = true; + signal_dspin_false_int_rsp_out[x][y][a][k].write = false; + signal_dspin_false_int_rsp_out[x][y][a][k].read = true; + } + + signal_dspin_false_ram_cmd_in[x][y][a].write = false; + signal_dspin_false_ram_cmd_in[x][y][a].read = true; + signal_dspin_false_ram_cmd_out[x][y][a].write = false; + signal_dspin_false_ram_cmd_out[x][y][a].read = true; + + signal_dspin_false_ram_rsp_in[x][y][a].write = false; + signal_dspin_false_ram_rsp_in[x][y][a].read = true; + signal_dspin_false_ram_rsp_out[x][y][a].write = false; + signal_dspin_false_ram_rsp_out[x][y][a].read = true; + } + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + + // simulation loop + struct timeval t1,t2; + gettimeofday(&t1, NULL); + + + for ( size_t n = 0; n < ncycles ; n += simul_period ) + { + // stats display + if( (n % 1000000) == 0) + { + gettimeofday(&t2, NULL); + + uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + + (uint64_t) t1.tv_usec / 1000; + uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + + (uint64_t) t2.tv_usec / 1000; + std::cerr << "### cycle = " << std::dec << n + << " / frequency = " + << (double) 1000000 / (double) (ms2 - ms1) << "Khz" + << std::endl; + + gettimeofday(&t1, NULL); + } + + // Monitor a specific address for one L1 cache + // clusters[0][0]->proc[0]->cache_monitor(0x600800ULL); + + // Monitor a specific address for one L2 cache + // clusters[0][0]->memc->cache_monitor( 0x600800ULL, false ); // full line + + // Monitor a specific address for one XRAM + // clusters[0][0]->xram->start_monitor( 0x600800ULL , 64); + + if ( debug_ok and (n > debug_from) ) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; + + // trace proc[debug_proc_id] + if ( debug_proc_id != 0xFFFFFFFF ) + { + size_t l = debug_proc_id & ((1<> P_WIDTH ; + size_t x = cluster_xy >> 4; + size_t y = cluster_xy & 0xF; + + clusters[x][y]->proc[l]->print_trace(0x1); + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; + clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); + +// clusters[x][y]->xicu->print_trace(l); +// std::ostringstream xicu_signame; +// xicu_signame << "[SIG]XICU_" << x << "_" << y; +// clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); + + clusters[x][y]->gcd->print_trace(); + clusters[x][y]->mwmr->print_trace(); + std::ostringstream mwmr_tgt_signame; + mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; + clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); + std::ostringstream mwmr_ini_signame; + mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; + clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); + + // local interrupts in cluster(x,y) + if( clusters[x][y]->signal_irq_memc.read() ) + std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y + << " ACTIVE" << std::endl; + + for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) + { + if( clusters[x][y]->signal_proc_it[c].read() ) + std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c + << " ACTIVE" << std::endl; + } + } + + // trace memc[debug_memc_id] + if ( debug_memc_id != 0xFFFFFFFF ) + { + size_t x = debug_memc_id >> 4; + size_t y = debug_memc_id & 0xF; + + clusters[x][y]->memc->print_trace(0); + std::ostringstream smemc_tgt; + smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; + clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); + std::ostringstream smemc_ini; + smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); + + clusters[x][y]->xram->print_trace(); + std::ostringstream sxram_tgt; + sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); + } + + + // trace XRAM and XRAM network routers in cluster[debug_xram_id] + if ( debug_xram_id != 0xFFFFFFFF ) + { + size_t x = debug_xram_id >> 4; + size_t y = debug_xram_id & 0xF; + + clusters[x][y]->xram->print_trace(); + std::ostringstream sxram_tgt; + sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); + + clusters[x][y]->ram_router_cmd->print_trace(); + clusters[x][y]->ram_router_rsp->print_trace(); + } + + // trace iob, iox and external peripherals + if ( debug_iob ) + { +// clusters[0][0]->iob->print_trace(); +// clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); +// clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); +// clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); +// signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); +// signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); + +// cdma->print_trace(); +// signal_vci_tgt_cdma.print_trace("[SIG]CDMA_TGT"); +// signal_vci_ini_cdma.print_trace("[SIG]CDMA_INI"); + +// brom->print_trace(); +// signal_vci_tgt_brom.print_trace("[SIG]BROM_TGT"); + +// mtty->print_trace(); +// signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); + + bdev->print_trace(); + signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); + signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + +// mnic->print_trace( 0x000 ); +// signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); + +// fbuf->print_trace(); +// signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); + +// iopi->print_trace(); +// signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); +// signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); +// iox_network->print_trace(); + + // interrupts + if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; + if (signal_irq_mtty_rx[0]) std::cout << "### IRQ_MTTY_RX[0] ACTIVE" << std::endl; + if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; + if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; + if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; + if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; + } + } + + sc_start(sc_core::sc_time(simul_period, SC_NS)); + } + return EXIT_SUCCESS; +} + +int sc_main (int argc, char *argv[]) +{ + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + + Index: /trunk/platforms/tsar_generic_mwmr/top.desc =================================================================== --- /trunk/platforms/tsar_generic_mwmr/top.desc (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/top.desc (revision 956) @@ -0,0 +1,86 @@ + +# -*- python -*- + +# VCI parameters +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 40 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# internal DSPIN network parameters +int_dspin_cmd_flit_size = 39 +int_dspin_rsp_flit_size = 32 + +# external DSPIN network parameters +ram_dspin_cmd_flit_size = 64 +ram_dspin_rsp_flit_size = 64 + +todo = Platform('caba', 'top.cpp', + + uses = [ + # cluster + Uses('caba:tsar_mwmr_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_int_cmd_width = int_dspin_cmd_flit_size, + dspin_int_rsp_width = int_dspin_rsp_flit_size, + dspin_ram_cmd_width = ram_dspin_cmd_flit_size, + dspin_ram_rsp_width = ram_dspin_rsp_flit_size), + + # IOX Network + Uses('caba:vci_iox_network', + cell_size = vci_cell_size_ext), + + # ROM + Uses('caba:vci_simple_rom', + cell_size = vci_cell_size_ext), + + # Frame Buffer + Uses('caba:vci_framebuffer', + cell_size = vci_cell_size_ext), + + # Block Device + Uses('caba:vci_block_device_tsar', + cell_size = vci_cell_size_ext), + + # NIC + Uses('caba:vci_multi_nic', + cell_size = vci_cell_size_ext), + + # Chained DMA + Uses('caba:vci_chbuf_dma', + cell_size = vci_cell_size_ext), + + # TTY + Uses('caba:vci_multi_tty', + cell_size = vci_cell_size_ext), + + # IOPIC + Uses('caba:vci_iopic', + cell_size = vci_cell_size_ext), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, + +) Index: /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/metadata/tsar_mwmr_cluster.sd =================================================================== --- /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/metadata/tsar_mwmr_cluster.sd (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/metadata/tsar_mwmr_cluster.sd (revision 956) @@ -0,0 +1,136 @@ + +# -*- python -*- + +Module('caba:tsar_mwmr_cluster', + classname = 'soclib::caba::TsarMwmrCluster', + + tmpl_parameters = [ + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + parameter.Int('dspin_int_cmd_width'), + parameter.Int('dspin_int_rsp_width'), + parameter.Int('dspin_ram_cmd_width'), + parameter.Int('dspin_ram_rsp_width'), + ], + + header_files = [ + '../source/include/tsar_mwmr_cluster.h', + ], + + implementation_files = [ + '../source/src/tsar_mwmr_cluster.cpp', + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + Uses('common:elf_file_loader'), + Uses('caba:coproc_signals'), + + # internal network components + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_int_cmd_width'), + dspin_out_width = parameter.Reference('dspin_int_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + memc_dspin_in_width = parameter.Reference('dspin_int_rsp_width'), + memc_dspin_out_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_mwmr_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:coproc_gcd'), + + Uses('caba:vci_local_crossbar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_ram_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_int_rsp_width')), + + # RAM network components + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_ext'), + dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_ext'), + dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_ram_cmd_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + # IOX network components + Uses('caba:vci_io_bridge', + iob_cell_size_int = parameter.Reference('vci_data_width_int'), + iob_cell_size_ext = parameter.Reference('vci_data_width_ext')), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + + Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], + dspin_data_size = parameter.Reference('dspin_int_cmd_width')), + Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], + dspin_data_size = parameter.Reference('dspin_int_cmd_width')), + Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], + dspin_data_size = parameter.Reference('dspin_int_rsp_width')), + Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], + dspin_data_size = parameter.Reference('dspin_int_rsp_width')), + + Port('caba:dspin_output', 'p_ram_cmd_out', [4], + dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), + Port('caba:dspin_input', 'p_ram_cmd_in', [4], + dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), + Port('caba:dspin_output', 'p_ram_rsp_out', [4], + dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), + Port('caba:dspin_input', 'p_ram_rsp_in', [4], + dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), + ], +) + + Index: /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/source/include/tsar_mwmr_cluster.h =================================================================== --- /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/source/include/tsar_mwmr_cluster.h (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/source/include/tsar_mwmr_cluster.h (revision 956) @@ -0,0 +1,269 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_mwmr_cluster.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : april 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_MWMR_CLUSTER_H +#define SOCLIB_CABA_TSAR_MWMR_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_xicu.h" +#include "vci_local_crossbar.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "dspin_router.h" +#include "virtual_dspin_router.h" +#include "vci_mwmr_dma.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_io_bridge.h" +#include "coproc_gcd.h" +#include "coproc_signals.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template +class TsarMwmrCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + + public: + + // Ports + sc_in p_clk; + sc_in p_resetn; + + // Thes two ports are used to connect IOB to IOX nework in top cell + soclib::caba::VciInitiator* p_vci_iob_iox_ini; + soclib::caba::VciTarget* p_vci_iob_iox_tgt; + + // These arrays of ports are used to connect the INT & RAM networks + soclib::caba::DspinOutput** p_dspin_int_cmd_out; + soclib::caba::DspinInput** p_dspin_int_cmd_in; + soclib::caba::DspinOutput** p_dspin_int_rsp_out; + soclib::caba::DspinInput** p_dspin_int_rsp_in; + + soclib::caba::DspinOutput* p_dspin_ram_cmd_out; + soclib::caba::DspinInput* p_dspin_ram_cmd_in; + soclib::caba::DspinOutput* p_dspin_ram_rsp_out; + soclib::caba::DspinInput* p_dspin_ram_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_it[16]; + sc_signal signal_irq_memc; + sc_signal signal_irq_mwmr; + + // Coprocessor signals + CoprocSignals signal_to_coproc[8]; + CoprocSignals signal_from_coproc[8]; + sc_signal signal_config_coproc[8]; + sc_signal signal_status_coproc[8]; + + // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars + DspinSignals signal_int_dspin_cmd_l2g_d; + DspinSignals signal_int_dspin_cmd_g2l_d; + DspinSignals signal_int_dspin_m2p_l2g_c; + DspinSignals signal_int_dspin_m2p_g2l_c; + DspinSignals signal_int_dspin_clack_l2g_c; + DspinSignals signal_int_dspin_clack_g2l_c; + DspinSignals signal_int_dspin_rsp_l2g_d; + DspinSignals signal_int_dspin_rsp_g2l_d; + DspinSignals signal_int_dspin_p2m_l2g_c; + DspinSignals signal_int_dspin_p2m_g2l_c; + + // INT network VCI signals between VCI components and VCI local crossbar + VciSignals signal_int_vci_ini_proc[8]; + VciSignals signal_int_vci_ini_mwmr; + VciSignals signal_int_vci_ini_iobx; + + VciSignals signal_int_vci_tgt_memc; + VciSignals signal_int_vci_tgt_xicu; + VciSignals signal_int_vci_tgt_mwmr; + VciSignals signal_int_vci_tgt_iobx; + + VciSignals signal_int_vci_l2g; + VciSignals signal_int_vci_g2l; + + // Coherence DSPIN signals between DSPIN local crossbars and CC components + DspinSignals signal_int_dspin_m2p_memc; + DspinSignals signal_int_dspin_clack_memc; + DspinSignals signal_int_dspin_p2m_memc; + DspinSignals signal_int_dspin_m2p_proc[8]; + DspinSignals signal_int_dspin_clack_proc[8]; + DspinSignals signal_int_dspin_p2m_proc[8]; + + // RAM network VCI signals between VCI components and VCI/DSPIN wrappers + VciSignals signal_ram_vci_ini_memc; + VciSignals signal_ram_vci_ini_iobx; + VciSignals signal_ram_vci_tgt_xram; + + // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar + // and routers + DspinSignals signal_ram_dspin_cmd_xram_t; + DspinSignals signal_ram_dspin_rsp_xram_t; + DspinSignals signal_ram_dspin_cmd_memc_i; + DspinSignals signal_ram_dspin_rsp_memc_i; + DspinSignals signal_ram_dspin_cmd_iob_i; + DspinSignals signal_ram_dspin_rsp_iob_i; + DspinSignals signal_ram_dspin_cmd_xbar; + DspinSignals signal_ram_dspin_rsp_xbar; + DspinSignals signal_ram_dspin_cmd_false; + DspinSignals signal_ram_dspin_rsp_false; + + ////////////////////////////////////// + // Hardwate Components (pointers) + ////////////////////////////////////// + VciCcVCacheWrapper >* proc[8]; + + VciMemCache* memc; + + VciDspinInitiatorWrapper* memc_ram_wi; + + VciXicu* xicu; + + VciMwmrDma* mwmr; + + CoprocGcd* gcd; + + VciLocalCrossbar* int_xbar_d; + + VciDspinInitiatorWrapper* int_wi_gate_d; + + VciDspinTargetWrapper* int_wt_gate_d; + + DspinLocalCrossbar* int_xbar_m2p_c; + DspinLocalCrossbar* int_xbar_p2m_c; + DspinLocalCrossbar* int_xbar_clack_c; + + VirtualDspinRouter* int_router_cmd; + VirtualDspinRouter* int_router_rsp; + + VciSimpleRam* xram; + + VciDspinTargetWrapper* xram_ram_wt; + + DspinRouter* ram_router_cmd; + DspinRouter* ram_router_rsp; + + DspinLocalCrossbar* ram_xbar_cmd; + DspinLocalCrossbar* ram_xbar_rsp; + + + // IO Network Components (not instanciated in all clusters) + + VciIoBridge* iob; + + VciDspinInitiatorWrapper* iob_ram_wi; + + // cluster constructor + TsarMwmrCluster(sc_module_name insname, + size_t nb_procs, + size_t x, // x coordinate + size_t y, // y coordinate + size_t xmax, + size_t ymax, + + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_ext, + const soclib::common::MappingTable &mt_iox, + + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + size_t p_width, // p field bits + + size_t int_memc_tgt_id, + size_t int_xicu_tgt_id, + size_t int_mwmr_tgt_id, + size_t int_iobx_tgt_id, + + size_t int_proc_ini_id, + size_t int_mwmr_ini_id, + size_t int_iobx_ini_id, + + size_t ram_xram_tgt_id, + size_t ram_memc_ini_id, + size_t ram_iobx_ini_id, + + bool is_io, + size_t iox_iobx_tgt_id, + size_t iox_iobx_ini_id, + + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + size_t xcu_nb_inputs, + + const Loader &loader, // loader for XRAM + + uint32_t frozen_cycles, + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok, + bool iob0_debug_ok ); + + protected: + + SC_HAS_PROCESS(TsarMwmrCluster); + + void init(); + + +}; + +}} + +#endif + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 +// Index: /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/source/src/tsar_mwmr_cluster.cpp =================================================================== --- /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/source/src/tsar_mwmr_cluster.cpp (revision 956) +++ /trunk/platforms/tsar_generic_mwmr/tsar_mwmr_cluster/caba/source/src/tsar_mwmr_cluster.cpp (revision 956) @@ -0,0 +1,671 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_mwmr_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : april 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. +// These two clusters contain 6 extra components: +// - 1 vci_io_bridge (connected to the 3 networks. +// - 3 vci_dspin_wrapper for the IOB. +// - 2 dspin_local_crossbar for commands and responses. +////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_mwmr_cluster.h" + +#define tmpl(x) \ + template\ + x TsarMwmrCluster<\ + vci_param_int , vci_param_ext,\ + dspin_int_cmd_width, dspin_int_rsp_width,\ + dspin_ram_cmd_width, dspin_ram_rsp_width> + +namespace soclib { namespace caba { + +////////////////////////////////////////////////////////////////////////// +// Constructor +////////////////////////////////////////////////////////////////////////// +tmpl(/**/)::TsarMwmrCluster( +////////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + size_t x_id, + size_t y_id, + size_t xmax, + size_t ymax, + + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_ram, + const soclib::common::MappingTable &mt_iox, + + size_t x_width, + size_t y_width, + size_t l_width, + size_t p_width, + + size_t int_memc_tgt_id, // local index + size_t int_xicu_tgt_id, // local index + size_t int_mwmr_tgt_id, // local index + size_t int_iobx_tgt_id, // local index + + size_t int_proc_ini_id, // local index + size_t int_mwmr_ini_id, // local index + size_t int_iobx_ini_id, // local index + + size_t ram_xram_tgt_id, // local index + size_t ram_memc_ini_id, // local index + size_t ram_iobx_ini_id, // local index + + bool is_io, // (IOB)? + size_t iox_iobx_tgt_id, // local_index + size_t iox_iobx_ini_id, // local index + + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + size_t xcu_nb_inputs, + + const Loader &loader, + + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok, + bool iob_debug_ok ) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") +{ + assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); + + size_t cluster_id = (x_id<<4) + y_id; + + // Vectors of DSPIN ports for inter-cluster communications + p_dspin_int_cmd_in = alloc_elems >("p_int_cmd_in", 4, 3); + p_dspin_int_cmd_out = alloc_elems >("p_int_cmd_out", 4, 3); + p_dspin_int_rsp_in = alloc_elems >("p_int_rsp_in", 4, 2); + p_dspin_int_rsp_out = alloc_elems >("p_int_rsp_out", 4, 2); + + p_dspin_ram_cmd_in = alloc_elems >("p_ext_cmd_in", 4); + p_dspin_ram_cmd_out = alloc_elems >("p_ext_cmd_out", 4); + p_dspin_ram_rsp_in = alloc_elems >("p_ext_rsp_in", 4); + p_dspin_ram_rsp_out = alloc_elems >("p_ext_rsp_out", 4); + + // VCI ports from IOB to IOX network (only in IO clusters) + if ( is_io ) + { + p_vci_iob_iox_ini = new soclib::caba::VciInitiator; + p_vci_iob_iox_tgt = new soclib::caba::VciTarget; + } + + ///////////////////////////////////////////////////////////////////////////// + // Hardware components + ///////////////////////////////////////////////////////////////////////////// + + //////////// PROCS + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream s_proc; + s_proc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper >( + s_proc.str().c_str(), + (cluster_id << p_width) + p, // GLOBAL PROC_ID + mt_int, // Mapping Table INT network + IntTab(cluster_id,p), // SRCID + (cluster_id << l_width) + p, // CC_GLOBAL_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways, l1_i_sets, 16, // ICACHE size + l1_d_ways, l1_d_sets, 16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + } + + /////////// MEMC + std::ostringstream s_memc; + s_memc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + s_memc.str().c_str(), + mt_int, // Mapping Table INT network + mt_ram, // Mapping Table RAM network + IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network + IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network + x_width, // number of bits for x coordinate + y_width, // number of bits for y coordinate + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + 8, // INVALIDATE TABLE DEPTH + debug_start_cycle, + memc_debug_ok ); + + std::ostringstream s_wi_memc; + s_wi_memc << "memc_wi_" << x_id << "_" << y_id; + memc_ram_wi = new VciDspinInitiatorWrapper( + s_wi_memc.str().c_str(), + x_width + y_width + l_width); + + /////////// XICU + std::ostringstream s_xicu; + s_xicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + s_xicu.str().c_str(), + mt_int, // mapping table INT network + IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space + xcu_nb_inputs, // number of timer IRQs + xcu_nb_inputs, // number of hard IRQs + xcu_nb_inputs, // number of soft IRQs + 16); // number of output IRQs + + //////////// MWMR controller + std::ostringstream s_mwmr; + s_mwmr << "mwmr_" << x_id << "_" << y_id; + mwmr = new VciMwmrDma( + s_mwmr.str().c_str(), + mt_int, + IntTab(cluster_id, int_mwmr_ini_id), // SRCID + IntTab(cluster_id, int_mwmr_tgt_id), // TGTID + 2, // nb to_coproc ports + 1, // nb from_coproc ports + 1, // nb config registers + 0, // nb status registers + 64 ); // burst size (bytes) + + /////////// GCD coprocessor + std::ostringstream s_gcd; + s_gcd << "gcd_" << x_id << "_" << y_id; + gcd = new CoprocGcd( + s_gcd.str().c_str(), + 64 ); // burst size (bytes) + + + /////////// Direct LOCAL_XBAR(S) + size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; + size_t nb_direct_targets = is_io ? 4 : 3; + + std::ostringstream s_int_xbar_d; + s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; + int_xbar_d = new VciLocalCrossbar( + s_int_xbar_d.str().c_str(), + mt_int, // mapping table + cluster_id, // cluster id + nb_direct_initiators, // number of local initiators + nb_direct_targets, // number of local targets + 0 ); // default target + + std::ostringstream s_int_dspin_ini_wrapper_gate_d; + s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" + << x_id << "_" << y_id; + int_wi_gate_d = new VciDspinInitiatorWrapper( + s_int_dspin_ini_wrapper_gate_d.str().c_str(), + x_width + y_width + l_width); + + std::ostringstream s_int_dspin_tgt_wrapper_gate_d; + s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" + << x_id << "_" << y_id; + int_wt_gate_d = new VciDspinTargetWrapper( + s_int_dspin_tgt_wrapper_gate_d.str().c_str(), + x_width + y_width + l_width); + + //////////// Coherence LOCAL_XBAR(S) + std::ostringstream s_int_xbar_m2p_c; + s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; + int_xbar_m2p_c = new DspinLocalCrossbar( + s_int_xbar_m2p_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, // several dests + 1, // number of local sources + nb_procs, // number of local dests + 2, 2, // fifo depths + true, // pseudo CMD + false, // no routing table + true ); // broacast + + std::ostringstream s_int_xbar_p2m_c; + s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; + int_xbar_p2m_c = new DspinLocalCrossbar( + s_int_xbar_p2m_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // only one dest + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // pseudo RSP + false, // no routing table + false ); // no broacast + + std::ostringstream s_int_xbar_clack_c; + s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; + int_xbar_clack_c = new DspinLocalCrossbar( + s_int_xbar_clack_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 1, 1, // fifo depths + true, // CMD + false, // no routing table + false); // broadcast + + ////////////// INT ROUTER(S) + std::ostringstream s_int_router_cmd; + s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; + int_router_cmd = new VirtualDspinRouter( + s_int_router_cmd.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 3, // nb virtual channels + 4,4); // input & output fifo depths + + std::ostringstream s_int_router_rsp; + s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; + int_router_rsp = new VirtualDspinRouter( + s_int_router_rsp.str().c_str(), + x_id,y_id, // router coordinates in mesh + x_width, y_width, // x & y fields width + 2, // nb virtual channels + 4,4); // input & output fifo depths + + ////////////// XRAM + std::ostringstream s_xram; + s_xram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + s_xram.str().c_str(), + IntTab(cluster_id, ram_xram_tgt_id), + mt_ram, + loader, + xram_latency); + + std::ostringstream s_wt_xram; + s_wt_xram << "xram_wt_" << x_id << "_" << y_id; + xram_ram_wt = new VciDspinTargetWrapper( + s_wt_xram.str().c_str(), + x_width + y_width + l_width); + + ///////////// RAM ROUTER(S) + std::ostringstream s_ram_router_cmd; + s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; + ram_router_cmd = new DspinRouter( + s_ram_router_cmd.str().c_str(), + x_id, y_id, // router coordinates in mesh + x_width, // x field width in first flit + y_width, // y field width in first flit + 4, 4); // input & output fifo depths + + std::ostringstream s_ram_router_rsp; + s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; + ram_router_rsp = new DspinRouter( + s_ram_router_rsp.str().c_str(), + x_id, y_id, // coordinates in mesh + x_width, // x field width in first flit + y_width, // y field width in first flit + 4, 4); // input & output fifo depths + + + ////////////////////// I/O CLUSTER ONLY /////////////////////// + if ( is_io ) + { + /////////// IO_BRIDGE + std::ostringstream s_iob; + s_iob << "iob_" << x_id << "_" << y_id; + iob = new VciIoBridge( + s_iob.str().c_str(), + mt_ram, // EXT network maptab + mt_int, // INT network maptab + mt_iox, // IOX network maptab + IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID + IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID + IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID + IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID + 16, // cache line words + 8, // IOTLB ways + 8, // IOTLB sets + debug_start_cycle, + iob_debug_ok ); + + std::ostringstream s_iob_ram_wi; + s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; + iob_ram_wi = new VciDspinInitiatorWrapper( + s_iob_ram_wi.str().c_str(), + vci_param_int::S); + + std::ostringstream s_ram_xbar_cmd; + s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; + ram_xbar_cmd = new DspinLocalCrossbar( + s_ram_xbar_cmd.str().c_str(), // name + mt_ram, // mapping table + x_id, y_id, // x, y + x_width, y_width, l_width, // x_width, y_width, l_width + 2, 0, // local inputs, local outputs + 2, 2, // in fifo, out fifo depths + true, // is cmd ? + false, // use routing table ? + false); // support broadcast ? + + std::ostringstream s_ram_xbar_rsp; + s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; + ram_xbar_rsp = new DspinLocalCrossbar( + s_ram_xbar_rsp.str().c_str(), // name + mt_ram, // mapping table + x_id, y_id, // x, y + x_width, y_width, l_width, // x_width, y_width, l_width + 0, 2, // local inputs, local outputs + 2, 2, // in fifo, out fifo depths + false, // is cmd ? + true, // use routing table ? + false); // support broadcast ? + } // end if IO + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + // on coherence network : local srcid[proc] in [0...nb_procs-1] + // : local srcid[memc] = nb_procs + + //////////////////////// internal CMD & RSP routers + int_router_cmd->p_clk (this->p_clk); + int_router_cmd->p_resetn (this->p_resetn); + int_router_rsp->p_clk (this->p_clk); + int_router_rsp->p_resetn (this->p_resetn); + + for (int i = 0; i < 4; i++) + { + for(int k = 0; k < 3; k++) + { + int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); + int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); + } + + for(int k = 0; k < 2; k++) + { + int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); + int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); + } + } + + // local ports + int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); + int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); + int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); + int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); + int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); + int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); + + int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); + int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); + int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); + int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); + + std::cout << " - Connected : CMD & RSP routers" << std::endl; + + ///////////////////// CMD DSPIN local crossbar direct + int_xbar_d->p_clk (this->p_clk); + int_xbar_d->p_resetn (this->p_resetn); + int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); + int_xbar_d->p_target_to_up (signal_int_vci_g2l); + + int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); + int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); + int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr); + int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); + + if ( is_io ) + { + int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); + int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); + } + + int_wi_gate_d->p_clk (this->p_clk); + int_wi_gate_d->p_resetn (this->p_resetn); + int_wi_gate_d->p_vci (signal_int_vci_l2g); + int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); + int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); + + int_wt_gate_d->p_clk (this->p_clk); + int_wt_gate_d->p_resetn (this->p_resetn); + int_wt_gate_d->p_vci (signal_int_vci_g2l); + int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); + int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); + + ////////////////////// M2P DSPIN local crossbar coherence + int_xbar_m2p_c->p_clk (this->p_clk); + int_xbar_m2p_c->p_resetn (this->p_resetn); + int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); + int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); + int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); + + ////////////////////////// P2M DSPIN local crossbar coherence + int_xbar_p2m_c->p_clk (this->p_clk); + int_xbar_p2m_c->p_resetn (this->p_resetn); + int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); + int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); + int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); + + ////////////////////// CLACK DSPIN local crossbar coherence + int_xbar_clack_c->p_clk (this->p_clk); + int_xbar_clack_c->p_resetn (this->p_resetn); + int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); + int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); + int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); + + std::cout << " - Connected : local crossbars" << std::endl; + + /////////////////////////////////// GCD coprocessor + gcd->p_clk (this->p_clk); + gcd->p_resetn (this->p_resetn); + gcd->p_opa (signal_to_coproc[0]); + gcd->p_opb (signal_to_coproc[1]); + gcd->p_res (signal_from_coproc[0]); + gcd->p_config (signal_config_coproc[0]); + + std::cout << " - Connected : GCD" << std::endl; + + /////////////////////////////////// MWMR controler + mwmr->p_clk (this->p_clk); + mwmr->p_resetn (this->p_resetn); + mwmr->p_vci_target (signal_int_vci_tgt_mwmr); + mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); + mwmr->p_to_coproc[0] (signal_to_coproc[0]); + mwmr->p_to_coproc[1] (signal_to_coproc[1]); + mwmr->p_from_coproc[0] (signal_from_coproc[0]); + mwmr->p_config[0] (signal_config_coproc[0]); + mwmr->p_irq (signal_irq_mwmr); + + std::cout << " - Connected : MWMR" << std::endl; + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_int_vci_ini_proc[p]); + proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); + proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); + proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); + + for ( size_t j = 0 ; j < 6 ; j++) + { + if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); + else proc[p]->p_irq[j] (signal_false); + } + } + + std::cout << " - Connected : processors" << std::endl; + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_int_vci_tgt_xicu); + for ( size_t i=0 ; i < 16 ; i++) + { + xicu->p_irq[i] (signal_proc_it[i]); + } + for ( size_t i=0 ; i < xcu_nb_inputs ; i++) + { + if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); + else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr); + else xicu->p_hwi[i] (signal_false); + } + + std::cout << " - Connected : XCU" << std::endl; + + ///////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_ram_vci_ini_memc); + memc->p_vci_tgt (signal_int_vci_tgt_memc); + memc->p_dspin_p2m (signal_int_dspin_p2m_memc); + memc->p_dspin_m2p (signal_int_dspin_m2p_memc); + memc->p_dspin_clack (signal_int_dspin_clack_memc); + memc->p_irq (signal_irq_memc); + + // wrapper to RAM network + memc_ram_wi->p_clk (this->p_clk); + memc_ram_wi->p_resetn (this->p_resetn); + memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); + memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); + memc_ram_wi->p_vci (signal_ram_vci_ini_memc); + + std::cout << " - Connected : MEMC" << std::endl; + + //////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_ram_vci_tgt_xram); + + // wrapper to RAM network + xram_ram_wt->p_clk (this->p_clk); + xram_ram_wt->p_resetn (this->p_resetn); + xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); + xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); + xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); + + //////////////////////////// RAM network CMD & RSP routers + ram_router_cmd->p_clk (this->p_clk); + ram_router_cmd->p_resetn (this->p_resetn); + ram_router_rsp->p_clk (this->p_clk); + ram_router_rsp->p_resetn (this->p_resetn); + for( size_t n=0 ; n<4 ; n++) + { + ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); + ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); + ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); + ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); + } + + ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); + ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); + + if ( is_io ) + { + ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); + ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); + } + else + { + ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); + ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); + } + + ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. + if ( is_io ) + { + // IO bridge + iob->p_clk (this->p_clk); + iob->p_resetn (this->p_resetn); + iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); + iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); + iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); + iob->p_vci_ini_int (signal_int_vci_ini_iobx); + iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); + + // initiator wrapper to RAM network + iob_ram_wi->p_clk (this->p_clk); + iob_ram_wi->p_resetn (this->p_resetn); + iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); + iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); + iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); + + // crossbar between MEMC and IOB to RAM network + ram_xbar_cmd->p_clk (this->p_clk); + ram_xbar_cmd->p_resetn (this->p_resetn); + ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); + ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); + ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); + ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); + + ram_xbar_rsp->p_clk (this->p_clk); + ram_xbar_rsp->p_resetn (this->p_resetn); + ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); + ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); + ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); + ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); + } + + SC_METHOD(init); + +} // end constructor + +tmpl(void)::init() +{ + signal_ram_dspin_cmd_false.write = false; + signal_ram_dspin_rsp_false.read = true; +} // end init + +}} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 +