Index: trunk/platforms/tsar_mono_fpga/Makefile =================================================================== --- trunk/platforms/tsar_mono_fpga/Makefile (revision 957) +++ trunk/platforms/tsar_mono_fpga/Makefile (revision 957) @@ -0,0 +1,12 @@ +simul.x: top.cpp top.desc hard_config.h + soclib-cc -P -p top.desc -I. -o simul.x + +.PHONY: tags cscope.out +cscope.out tags: top.desc + soclib-cc -p $< --tags --tags-type=cscope --tags-output=cscope.out + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x term* tty* ext* temp + +.PHONY: simul.x Index: trunk/platforms/tsar_mono_fpga/arch.py =================================================================== --- trunk/platforms/tsar_mono_fpga/arch.py (revision 957) +++ trunk/platforms/tsar_mono_fpga/arch.py (revision 957) @@ -0,0 +1,320 @@ +#!/usr/bin/env python + +from math import log, ceil +from mapping import * + +############################################################################### +# file : arch.py (for the tsar_monocluster_fpga architecture) +# date : March 2015 +# author : Cesar Fuguet +############################################################################### +# This file contains a mapping generator for the "tsar_mono_fpga" +# platform. +# This includes both the hardware architecture (clusters, processors, +# peripherals, physical space segmentation) and the mapping of all boot +# and kernel objects (global vsegs). +# +# It is inspired on the tsar_mono_fpga platform but includes a ROM in the +# cluster. +# +# The others hardware parameters are: +# - fbf_width : frame_buffer width = frame_buffer heigth +# - nb_ttys : number of TTY channels +# - nb_nics : number of NIC channels +# - nb_cmas : number of CMA channels +# - irq_per_proc : number of input IRQs per processor +# - use_ramdisk : use a RAMDISK when True +# - peri_increment : address increment for replicated peripherals +############################################################################### + +######################## +def arch( x_size = 1, + y_size = 1, + nb_procs = 2, + nb_ttys = 1, + fbf_width = 480 ): + + ### define architecture constants + + x_io = 0 + y_io = 0 + x_width = 4 + y_width = 4 + p_width = 2 + paddr_width = 40 + irq_per_proc = 4 + use_ramdisk = False + peri_increment = 0x10000 # distributed peripherals vbase increment + reset_address = 0xFF000000 # wired preloader pbase address + use_backup_peri = True + + ### parameters checking + + assert( nb_procs <= (1 << p_width) ) + assert( (x_size == 1) and (y_size == 1) ); + + ### define type and name + + platform_type = 'tsar_fpga' + platform_name = '%s_%d' % (platform_type, nb_procs ) + + ### define physical segments replicated in all clusters + ### the base address is extended by the cluster_xy (8 bits) + + ram_base = 0x00000000 + ram_size = 0x8000000 # 128 Mbytes + + xcu_base = 0xF0000000 + xcu_size = 0x1000 # 4 Kbytes + + mmc_base = 0xF1000000 + mmc_size = 0x1000 # 4 Kbytes + + rom_base = 0xFF000000 + rom_size = 0x10000 # 64 Kbytes + + bdv_base = 0xF2000000 + bdv_size = 0x1000 # 4kbytes + + tty_base = 0xF4000000 + tty_size = 0x4000 # 16 Kbytes + + fbf_base = 0xF3000000 + fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes + + ### define preloader & bootloader vsegs base addresses and sizes + ### We want to pack these 5 vsegs in the same big page + ### => boot cost is one BPP in cluster[0][0] + + preloader_vbase = reset_address # ident + preloader_size = 0x00010000 # 64 Kbytes + + boot_mapping_vbase = 0x00010000 # ident + boot_mapping_size = 0x00080000 # 512 Kbytes + + boot_code_vbase = 0x00090000 # ident + boot_code_size = 0x00040000 # 256 Kbytes + + boot_data_vbase = 0x000D0000 # ident + boot_data_size = 0x000B0000 # 704 Kbytes + + boot_stack_vbase = 0x00180000 # ident + boot_stack_size = 0x00080000 # 512 Kbytes + + ### define ramdisk vseg / must be identity mapping in cluster[0][0] + ### occupies 15 BPP after the boot + ramdisk_vbase = 0x00200000 + ramdisk_size = 0x02000000 # 32 Mbytes + + ### define kernel vsegs base addresses and sizes + ### code, init, ptab, heap & sched vsegs are replicated in all clusters. + ### data & uncdata vsegs are only mapped in cluster[0][0]. + + kernel_code_vbase = 0x80000000 + kernel_code_size = 0x00100000 # 1 Mbytes per cluster + + kernel_init_vbase = 0x80100000 + kernel_init_size = 0x00100000 # 1 Mbytes per cluster + + kernel_data_vbase = 0x90000000 + kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0][0] + + kernel_ptab_vbase = 0xE0000000 + kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster + + kernel_heap_vbase = 0xD0000000 + kernel_heap_size = 0x00200000 # 2 Mbytes per cluster + + kernel_sched_vbase = 0xA0000000 + kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per proc per cluster + + ##################### + ### create mapping + ##################### + + mapping = Mapping( name = platform_name, + x_size = x_size, + y_size = y_size, + nprocs = nb_procs, + x_width = x_width, + y_width = y_width, + p_width = p_width, + paddr_width = paddr_width, + coherence = True, + irq_per_proc = irq_per_proc, + use_ramdisk = use_ramdisk, + x_io = x_io, + y_io = y_io, + peri_increment = peri_increment, + reset_address = reset_address, + ram_base = ram_base, + ram_size = ram_size ) + + ########################### + ### Hardware Description + ########################### + + ### components replicated in all clusters but the upper row + ram = mapping.addRam( 'RAM', base = ram_base, size = ram_size ) + + xcu = mapping.addPeriph( 'XCU', base = xcu_base, size = xcu_size, + ptype = 'XCU', channels = nb_procs * irq_per_proc, + arg = 16 ) + + mmc = mapping.addPeriph( 'MMC', base = mmc_base, size = mmc_size, + ptype = 'MMC' ) + + mapping.addIrq( xcu, index = 8 , isrtype = 'ISR_MMC' ) + + for p in xrange ( nb_procs ): mapping.addProc( 0, 0, p ) + + bdv = mapping.addPeriph( 'BDV0', base = bdv_base, size = bdv_size, + ptype = 'IOC', subtype = 'BDV' ) + + mapping.addIrq( xcu, index = 9 , isrtype = 'ISR_BDV' ) + + tty = mapping.addPeriph( 'TTY0', base = tty_base, size = tty_size, + ptype = 'TTY', channels = nb_ttys ) + + mapping.addIrq( xcu, index = 10, isrtype = 'ISR_TTY_RX' ) + + rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, + ptype = 'ROM' ) + + fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, + ptype = 'FBF', arg = fbf_width ) + + ################################### + ### boot & kernel vsegs mapping + ################################### + + ### global vsegs for preloader & boot_loader are mapped in cluster[0][0] + ### => same flags CXW_ / identity mapping / non local / big page + + mapping.addGlobal( 'seg_preloader', preloader_vbase, preloader_size, + 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True, local = False, big = True ) + + mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, + 'CXW_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', + identity = True, local = False, big = True ) + + mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, + 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True, local = False, big = True ) + + mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, + 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True, local = False, big = True ) + + mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, + 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True, local = False, big = True ) + + ### global vseg for RAM-DISK in cluster[0][0] + ### identity mapping / non local / big pages + if use_ramdisk: + + mapping.addGlobal( 'seg_ramdisk', ramdisk_vbase, ramdisk_size, + 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', + identity = True, local = True, big = True ) + + ### global vsegs kernel_code, kernel_init : local / big page + ### replicated in all clusters containing processors + ### same content => same name / same vbase + mapping.addGlobal( 'seg_kernel_code', + kernel_code_vbase, kernel_code_size, + 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', + binpath = 'build/kernel/kernel.elf', + local = True, big = True ) + + mapping.addGlobal( 'seg_kernel_init', + kernel_init_vbase, kernel_init_size, + 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', + binpath = 'build/kernel/kernel.elf', + local = True, big = True ) + + ### global vseg kernel_data: non local / big page + ### Only mapped in cluster[0][0] + mapping.addGlobal( 'seg_kernel_data', + kernel_data_vbase, kernel_data_size, + 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', + binpath = 'build/kernel/kernel.elf', + local = False, big = True ) + + ### Global vsegs kernel_ptab_x_y: non local / big page + ### replicated in all clusters containing processors + ### different content => name & vbase indexed by (x,y) + mapping.addGlobal( 'seg_kernel_ptab', + kernel_ptab_vbase, kernel_ptab_size, + 'CXW_', vtype = 'PTAB', x = 0, y = 0, pseg = 'RAM', + local = False, big = True ) + + ### global vsegs kernel_heap_x_y : non local / big pages + ### distributed in all clusters containing processors + ### different content => name & vbase indexed by (x,y) + mapping.addGlobal( 'seg_kernel_heap', + kernel_heap_vbase, kernel_heap_size, + 'C_W_', vtype = 'HEAP', x = 0 , y = 0 , pseg = 'RAM', + local = False, big = True ) + + ### global vsegs for external peripherals: non local / big page + ### only mapped in cluster_io + mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, + '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', + local = False, big = True ) + + mapping.addGlobal( 'seg_tty', tty_base, tty_size, + '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', + local = False, big = True ) + + mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, + '__W_', vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', + local = False, big = True ) + + ### global vsegs for internal peripherals : non local / small pages + ### allocated in all clusters containing processors + ### name and vbase indexed by (x,y) + mapping.addGlobal( 'seg_xcu', + xcu_base, xcu_size, + '__W_', vtype = 'PERI' , x = 0 , y = 0 , pseg = 'XCU', + local = False, big = False ) + + mapping.addGlobal( 'seg_mmc', + mmc_base, mmc_size, + '__W_', vtype = 'PERI' , x = 0 , y = 0 , pseg = 'MMC', + local = False, big = False ) + + ### global vsegs kernel_sched : non local / small pages + ### allocated in all clusters containing processors + ### different content => name & vbase indexed by (x,y) + mapping.addGlobal( 'seg_kernel_sched', + kernel_sched_vbase, kernel_sched_size, + 'C_W_', vtype = 'SCHED', x = 0, y = 0, pseg = 'RAM', + local = False, big = False ) + + return mapping + +########################## platform test ############################################# + +if __name__ == '__main__': + mapping = arch( x_size = 1, + y_size = 1, + nb_procs = 2 ) + +# print mapping.netbsd_dts() + + print mapping.xml() + +# print mapping.giet_vsegs() + + +# Local Variables: +# tab-width: 4; +# c-basic-offset: 4; +# c-file-offsets:((innamespace . 0)(inline-open . 0)); +# indent-tabs-mode: nil; +# End: +# +# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: trunk/platforms/tsar_mono_fpga/top.cpp =================================================================== --- trunk/platforms/tsar_mono_fpga/top.cpp (revision 957) +++ trunk/platforms/tsar_mono_fpga/top.cpp (revision 957) @@ -0,0 +1,515 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp (for tsar_mono_fpga) +// Author: Cesar Fuguet +// Copyright: UPMC/LIP6 +// Date : March 2015 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "tsar_fpga_cluster.h" +#include "vci_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "vci_multi_tty.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "alloc_elems.h" + +#include "hard_config.h" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#define USE_OPENMP _OPENMP + +#if USE_OPENMP +#include +#endif + +/////////////////////////////////////////////////// +// cluster index (from x,y coordinates) +/////////////////////////////////////////////////// + +#define cluster(x,y) ((y) + ((x) << Y_WIDTH)) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 +#define vci_address_width 40 +#define vci_plen_width 8 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + + +/////////////////////////////////////////////////////////////////////////////////////// +// Secondary Hardware Parameters +/////////////////////////////////////////////////////////////////////////////////////// + +#define XMAX X_SIZE // actual number of columns in 2D mesh +#define YMAX Y_SIZE // actual number of rows in 2D mesh + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" + +#define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +/////////////////////////////////////////////////////////////////////////////////////// +// DEBUG Parameters default values +/////////////////////////////////////////////////////////////////////////////////////// + +#define MAX_FROZEN_CYCLES 500000 + +/////////////////////////////////////////////////////////////////////////////////////// +// LOCAL TGTID & SRCID definition +// For all components: global TGTID = global SRCID = cluster_index +/////////////////////////////////////////////////////////////////////////////////////// + +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define XROM_TGTID 2 +#define MTTY_TGTID 3 +#define BDEV_TGTID 4 +#define FBUF_TGTID 5 + +#define BDEV_SRCID NB_PROCS_MAX + +bool stop_called = false; + +#define SIMULATION_PERIOD 5000000 + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + uint64_t ncycles = UINT64_MAX; // max simulated cycles + size_t threads = 1; // simulator's threads number + bool trace_ok = false; // trace activated + uint32_t trace_from = 0; // trace start cycle + bool trace_proc_ok = false; // detailed proc trace activated + size_t trace_memc_ok = false; // detailed memc trace activated + size_t trace_memc_id = 0; // index of memc to be traced + size_t trace_proc_id = 0; // index of proc to be traced + char soft_name[256] = ROM_SOFT_NAME; // pathname for ROM binary code + char disk_name[256] = BDEV_IMAGE_NAME; // pathname for DISK image + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // for debug + uint64_t simulation_period = SIMULATION_PERIOD; + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) + { + ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) + { + trace_ok = true; + trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0); + simulation_period = 1; + } + else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) + { + trace_memc_ok = true; + trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); + size_t x = trace_memc_id >> Y_WIDTH; + size_t y = trace_memc_id & ((1<> P_WIDTH ; + size_t x = cluster_xy >> Y_WIDTH; + size_t y = cluster_xy & ((1< signal_resetn("resetn"); + + //////////////////////////// + // Loader + //////////////////////////// + +#if USE_IOC_RDK + std::ostringstream ramdisk_name; + ramdisk_name << disk_name << "@" << std::hex << SEG_RDK_BASE << ":"; + soclib::common::Loader loader( soft_name, ramdisk_name.str().c_str() ); +#else + soclib::common::Loader loader( soft_name ); +#endif + + loader.memory_default(0x55); + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader( loader ); + + ////////////////////////////////////////////////////////////// + // cluster construction + ////////////////////////////////////////////////////////////// + TsarFpgaCluster fpga_cluster ( + "tsar_fpga_cluster", + NB_PROCS_MAX, + maptabd, maptabx, + RESET_ADDRESS, + X_WIDTH, Y_WIDTH, + vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MTTY_TGTID, + BDEV_TGTID, + XROM_TGTID, + disk_name, + MEMC_WAYS, MEMC_SETS, + L1_IWAYS, L1_ISETS, L1_DWAYS, L1_DSETS, + XRAM_LATENCY, + loader, + frozen_cycles, trace_from, + trace_proc_ok, trace_proc_id, + trace_memc_ok ); + + DspinSignals signal_dspin_bound_cmd_in; + DspinSignals signal_dspin_bound_cmd_out; + DspinSignals signal_dspin_bound_rsp_in; + DspinSignals signal_dspin_bound_rsp_out; + DspinSignals signal_dspin_bound_m2p_in; + DspinSignals signal_dspin_bound_m2p_out; + DspinSignals signal_dspin_bound_p2m_in; + DspinSignals signal_dspin_bound_p2m_out; + DspinSignals signal_dspin_bound_cla_in; + DspinSignals signal_dspin_bound_cla_out; + + // Cluster clock & reset + fpga_cluster.p_clk(signal_clk); + fpga_cluster.p_resetn(signal_resetn); + fpga_cluster.p_cmd_in(signal_dspin_bound_cmd_in); + fpga_cluster.p_cmd_out(signal_dspin_bound_cmd_out); + fpga_cluster.p_rsp_in(signal_dspin_bound_rsp_in); + fpga_cluster.p_rsp_out(signal_dspin_bound_rsp_out); + fpga_cluster.p_m2p_in(signal_dspin_bound_m2p_in); + fpga_cluster.p_m2p_out(signal_dspin_bound_m2p_out); + fpga_cluster.p_p2m_in(signal_dspin_bound_p2m_in); + fpga_cluster.p_p2m_out(signal_dspin_bound_p2m_out); + fpga_cluster.p_cla_in(signal_dspin_bound_cla_in); + fpga_cluster.p_cla_out(signal_dspin_bound_cla_out); + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // set cluster gateway signals default values + signal_dspin_bound_cmd_in.write = false; + signal_dspin_bound_cmd_in.read = true; + signal_dspin_bound_cmd_out.write = false; + signal_dspin_bound_cmd_out.read = true; + + signal_dspin_bound_rsp_in.write = false; + signal_dspin_bound_rsp_in.read = true; + signal_dspin_bound_rsp_out.write = false; + signal_dspin_bound_rsp_out.read = true; + + signal_dspin_bound_m2p_in.write = false; + signal_dspin_bound_m2p_in.read = true; + signal_dspin_bound_m2p_out.write = false; + signal_dspin_bound_m2p_out.read = true; + + signal_dspin_bound_p2m_in.write = false; + signal_dspin_bound_p2m_in.read = true; + signal_dspin_bound_p2m_out.write = false; + signal_dspin_bound_p2m_out.read = true; + + signal_dspin_bound_cla_in.write = false; + signal_dspin_bound_cla_in.read = true; + signal_dspin_bound_cla_out.write = false; + signal_dspin_bound_cla_out.read = true; + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + // simulation loop + for (uint64_t n = 0; n < ncycles && !stop_called; n += simulation_period) + { + // trace display + if ( trace_ok and (n > trace_from) ) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ********************************************" << std::endl; + + if ( trace_proc_ok ) + { + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << trace_proc_id ; + fpga_cluster.proc[trace_proc_id]->print_trace(1); + fpga_cluster.signal_vci_ini_proc[trace_proc_id].print_trace(proc_signame.str()); + + fpga_cluster.xicu->print_trace(0); + fpga_cluster.signal_vci_tgt_xicu.print_trace("[SIG]XICU"); + + for (int p = 0; p < NB_PROCS_MAX; p++) + { + if ( fpga_cluster.signal_proc_irq[p*IRQ_PER_PROCESSOR].read() ) + { + std::cout << "### IRQ_PROC_" << p << std::endl; + } + } + } + + if ( trace_memc_ok ) + { + fpga_cluster.memc->print_trace(); + fpga_cluster.signal_vci_tgt_memc.print_trace("[SEG]MEMC"); + fpga_cluster.signal_vci_xram.print_trace("[SEG]XRAM"); + } + + fpga_cluster.bdev->print_trace(); + fpga_cluster.signal_vci_tgt_bdev.print_trace("[SIG]BDEV_0_0"); + fpga_cluster.signal_vci_ini_bdev.print_trace("[SIG]BDEV_0_0"); + } // end trace + + struct timeval t1,t2; + if (gettimeofday(&t1, NULL) != 0) return EXIT_FAILURE; + sc_start(sc_core::sc_time(simulation_period, SC_NS)); + if (gettimeofday(&t2, NULL) != 0) return EXIT_FAILURE; + + // stats display + if (!trace_ok) + { + uint64_t ms1 = (uint64_t)t1.tv_sec * 1000ULL + + (uint64_t)t1.tv_usec / 1000; + uint64_t ms2 = (uint64_t)t2.tv_sec * 1000ULL + + (uint64_t)t2.tv_usec / 1000; + std::cerr << "platform clock frequency " + << (double) simulation_period / (double) (ms2 - ms1) + << "Khz" << std::endl; + } + } + + return EXIT_SUCCESS; +} + +void handler(int dummy = 0) +{ + stop_called = true; + sc_stop(); +} + +void voidhandler(int dummy = 0) {} + +int sc_main (int argc, char *argv[]) +{ + signal(SIGINT, handler); + signal(SIGPIPE, voidhandler); + + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: trunk/platforms/tsar_mono_fpga/top.desc =================================================================== --- trunk/platforms/tsar_mono_fpga/top.desc (revision 957) +++ trunk/platforms/tsar_mono_fpga/top.desc (revision 957) @@ -0,0 +1,69 @@ + +# -*- python -*- + +# internal VCI parameters values +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 40 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 + +todo = Platform('caba', 'top.cpp', + + uses = [ + Uses('caba:tsar_fpga_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = vci_cell_size_int, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = vci_cell_size_int, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('caba:vci_local_crossbar', + cell_size = vci_cell_size_int), + + Uses('caba:vci_framebuffer', + cell_size = vci_cell_size_int), + + Uses('caba:vci_block_device_tsar', + cell_size = vci_cell_size_int), + + Uses('caba:vci_multi_tty', + cell_size = vci_cell_size_int), + + Uses('common:elf_file_loader'), + + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, +) Index: trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/metadata/tsar_fpga_cluster.sd =================================================================== --- trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/metadata/tsar_fpga_cluster.sd (revision 957) +++ trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/metadata/tsar_fpga_cluster.sd (revision 957) @@ -0,0 +1,100 @@ + +# -*- python -*- + +Module('caba:tsar_fpga_cluster', + classname = 'soclib::caba::TsarFpgaCluster', + tmpl_parameters = [ + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + ], + + header_files = [ '../source/include/tsar_fpga_cluster.h', ], + implementation_files = [ '../source/src/tsar_fpga_cluster.cpp', ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_cmd_width'), + dspin_out_width = parameter.Reference('dspin_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + memc_dspin_in_width = parameter.Reference('dspin_rsp_width'), + memc_dspin_out_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_local_crossbar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:vci_multi_tty', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_block_device_tsar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simple_rom', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('common:elf_file_loader'), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + + Port('caba:dspin_output', 'p_cmd_out', + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', + dspin_data_size = parameter.Reference('dspin_cmd_width')), + + Port('caba:dspin_output', 'p_rsp_out', + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', + dspin_data_size = parameter.Reference('dspin_rsp_width')), + + Port('caba:dspin_output', 'p_m2p_out', + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_m2p_in', + dspin_data_size = parameter.Reference('dspin_cmd_width')), + + Port('caba:dspin_output', 'p_p2m_out', + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_p2m_in', + dspin_data_size = parameter.Reference('dspin_rsp_width')), + + Port('caba:dspin_output', 'p_cla_out', + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cla_in', + dspin_data_size = parameter.Reference('dspin_cmd_width')), + ], +) + +# vim: ts=4 : sts=4 : sw=4 : et Index: trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/source/include/tsar_fpga_cluster.h =================================================================== --- trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/source/include/tsar_fpga_cluster.h (revision 957) +++ trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/source/include/tsar_fpga_cluster.h (revision 957) @@ -0,0 +1,150 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_fpga_cluster.h +// Author: Cesar Fuguet +// Copyright: UPMC/LIP6 +// Date : march 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +#ifndef SOCLIB_CABA_TSAR_FPGA_CLUSTER_H +#define SOCLIB_CABA_TSAR_FPGA_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_xicu.h" +#include "vci_local_crossbar.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "vci_multi_tty.h" +#include "vci_block_device_tsar.h" +#include "vci_simple_rom.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template class TsarFpgaCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + public: + + // Used in destructor + size_t m_nprocs; + + // Ports + sc_in p_clk; + sc_in p_resetn; + + soclib::caba::DspinOutput p_cmd_out; + soclib::caba::DspinInput p_cmd_in; + soclib::caba::DspinOutput p_rsp_out; + soclib::caba::DspinInput p_rsp_in; + soclib::caba::DspinOutput p_m2p_out; + soclib::caba::DspinInput p_m2p_in; + soclib::caba::DspinOutput p_p2m_out; + soclib::caba::DspinInput p_p2m_in; + soclib::caba::DspinOutput p_cla_out; + soclib::caba::DspinInput p_cla_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_irq[16]; + sc_signal signal_irq_mtty; + sc_signal signal_irq_memc; + sc_signal signal_irq_bdev; + + // Direct VCI signals + VciSignals signal_vci_ini_proc[4]; + VciSignals signal_vci_ini_bdev; + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_xrom; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_g2l; + VciSignals signal_vci_l2g; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_clack_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[4]; + DspinSignals signal_dspin_clack_proc[4]; + DspinSignals signal_dspin_p2m_proc[4]; + + // external RAM to MEMC VCI signal + VciSignals signal_vci_xram; + + // Components + VciCcVCacheWrapper >* proc[4]; + + VciMemCache* memc; + + VciXicu* xicu; + VciSimpleRam* xram; + VciMultiTty* mtty; + VciBlockDeviceTsar* bdev; + VciSimpleRom* xrom; + VciLocalCrossbar* xbar_cmd; + + VciDspinInitiatorWrapper* wi_gate; + + VciDspinTargetWrapper* wt_gate; + + DspinLocalCrossbar* xbar_m2p; + DspinLocalCrossbar* xbar_p2m; + DspinLocalCrossbar* xbar_cla; + + TsarFpgaCluster( sc_module_name insname, + size_t nb_procs, // processors + const soclib::common::MappingTable &mtd, // internal + const soclib::common::MappingTable &mtx, // external + uint32_t reset_address, // boot address + size_t x_width, size_t y_width, size_t l_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mtty, + size_t tgtid_bdev, + size_t tgtid_xrom, + const char* disk_pathname, + size_t memc_ways, size_t memc_sets, + size_t l1_i_ways, size_t l1_i_sets, + size_t l1_d_ways, size_t l1_d_sets, + size_t xram_latency, + const Loader &loader, + uint32_t frozen_cycles, + uint32_t trace_start_cycle, + bool trace_proc_ok, uint32_t trace_proc_id, + bool trace_memc_ok ); + + ~TsarFpgaCluster(); + +}; +}} + +#endif Index: trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/source/src/tsar_fpga_cluster.cpp =================================================================== --- trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/source/src/tsar_fpga_cluster.cpp (revision 957) +++ trunk/platforms/tsar_mono_fpga/tsar_fpga_cluster/caba/source/src/tsar_fpga_cluster.cpp (revision 957) @@ -0,0 +1,396 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_fpga_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : february 2014 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_fpga_cluster.h" + +namespace soclib { +namespace caba { + +//////////////////////////////////////////////////////////////////////////////////// +template TsarFpgaCluster::TsarFpgaCluster( + //////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtx, + uint32_t reset_address, + size_t x_width, size_t y_width, size_t l_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mtty, + size_t tgtid_bdev, + size_t tgtid_xrom, + const char* disk_pathname, + size_t memc_ways, size_t memc_sets, + size_t l1_i_ways, size_t l1_i_sets, + size_t l1_d_ways, size_t l1_d_sets, + size_t xram_latency, + const Loader &loader, + uint32_t frozen_cycles, + uint32_t trace_start_cycle, + bool trace_proc_ok, uint32_t trace_proc_id, + bool trace_memc_ok ) + : soclib::caba::BaseModule(insname), + m_nprocs(nb_procs), + p_clk("clk"), + p_resetn("resetn") + +{ + ///////////////////////////////////////////////////////////////////////////// + // Components definition and allocation + ///////////////////////////////////////////////////////////////////////////// + + // The processor is a MIPS32 wrapped in the GDB server + // the reset address is defined by the reset_address argument + typedef GdbServer mips_iss; + mips_iss::setResetAddress( reset_address ); + + for (size_t p = 0; p < nb_procs; p++) + { + bool trace_ok = trace_proc_ok and (trace_proc_id == p); + + std::ostringstream sproc; + sproc << "proc_" << p; + proc[p] = new VciCcVCacheWrapper ( + sproc.str().c_str(), + p, // GLOBAL PROC_ID + mtd, // Mapping Table + IntTab(0,p), // SRCID + p, // GLOBAL_CC_ID + 8, 8, // ITLB ways & sets + 8, 8, // DTLB ways & sets + l1_i_ways, l1_i_sets, 16, // ICACHE size + l1_d_ways, l1_d_sets, 16, // DCACHE size + 4, 4, // WBUF lines & words + x_width, y_width, + frozen_cycles, // max frozen cycles + trace_start_cycle, trace_ok ); + } + + ///////////////////////////////////////////////////////////////////////////// + memc = new VciMemCache( + "memc", + mtd, // Mapping Table direct space + mtx, // Mapping Table external space + IntTab(0), // SRCID external space + IntTab(0, tgtid_memc), // TGTID direct space + x_width, y_width, // Number of x,y bits in platform + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, 8, 8, // TRT, UPT, IVT DEPTH + trace_start_cycle, + trace_memc_ok ); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxram; + xram = new VciSimpleRam( + "xram", + IntTab(0), + mtx, + loader, + xram_latency); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxicu; + xicu = new VciXicu( + "xicu", + mtd, // mapping table + IntTab(0, tgtid_xicu), // TGTID_D + 16, // number of timer IRQs + 16, // number of hard IRQs + 16, // number of soft IRQs + 16 ); // number of output IRQs + + ///////////////////////////////////////////////////////////////////////////// + size_t nb_initiators = nb_procs + 1; + size_t nb_targets = 5; + + std::ostringstream s_xbar_cmd; + xbar_cmd = new VciLocalCrossbar( + s_xbar_cmd.str().c_str(), + mtd, // mapping table + 0, // cluster id + nb_initiators, // number of local initiators + nb_targets, // number of local targets + 0 ); // default target + + wi_gate = new VciDspinInitiatorWrapper( + "wi_gate", + x_width + y_width + l_width); + + wt_gate = new VciDspinTargetWrapper( + "wt_gate", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + xbar_m2p = new DspinLocalCrossbar( + "xbar_m2p", + mtd, // mapping table + 0, 0, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local dests + 2, 2, // fifo depths + true, // CMD + false, // don't use local routing table + true ); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_p2m = new DspinLocalCrossbar( + "xbar_p2m", + mtd, // mapping table + 0, 0, // cluster coordinates + x_width, y_width, 0, // l_width unused on p2m network + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_cla = new DspinLocalCrossbar( + "xbar_cla", + mtd, // mapping table + 0, 0, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local dests + 2, 2, // fifo depths + true, // CMD + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////// + bdev = new VciBlockDeviceTsar( + "bdev", + mtd, + IntTab(0, nb_procs), + IntTab(0, tgtid_bdev), + disk_pathname, + 512, + 64 ); // burst size + + ///////////////////////////////////////////// + mtty = new VciMultiTty( + "mtty", + IntTab(0, tgtid_mtty), + mtd, + "tty", NULL ); + + ///////////////////////////////////////////// + xrom = new VciSimpleRom( + "xrom", + IntTab(0, tgtid_xrom), + mtd, + loader, + 0 ); + + std::cout << std::endl; + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + // CMD DSPIN local crossbar direct + xbar_cmd->p_clk(this->p_clk); + xbar_cmd->p_resetn(this->p_resetn); + xbar_cmd->p_initiator_to_up(signal_vci_l2g); + xbar_cmd->p_target_to_up(signal_vci_g2l); + + xbar_cmd->p_to_target[tgtid_memc](signal_vci_tgt_memc); + xbar_cmd->p_to_target[tgtid_xicu](signal_vci_tgt_xicu); + xbar_cmd->p_to_target[tgtid_mtty](signal_vci_tgt_mtty); + xbar_cmd->p_to_target[tgtid_bdev](signal_vci_tgt_bdev); + xbar_cmd->p_to_target[tgtid_xrom](signal_vci_tgt_xrom); + + for (size_t p = 0; p < nb_procs; p++) + { + xbar_cmd->p_to_initiator[p](signal_vci_ini_proc[p]); + } + xbar_cmd->p_to_initiator[nb_procs](signal_vci_ini_bdev); + + wi_gate->p_clk(this->p_clk); + wi_gate->p_resetn(this->p_resetn); + wi_gate->p_vci(signal_vci_l2g); + wi_gate->p_dspin_cmd(p_cmd_out); + wi_gate->p_dspin_rsp(p_rsp_in); + + wt_gate->p_clk(this->p_clk); + wt_gate->p_resetn(this->p_resetn); + wt_gate->p_vci(signal_vci_g2l); + wt_gate->p_dspin_cmd(p_cmd_in); + wt_gate->p_dspin_rsp(p_rsp_out); + + std::cout << " - CMD & RSP Direct crossbar connected" << std::endl; + + // M2P DSPIN local crossbar coherence + xbar_m2p->p_clk(this->p_clk); + xbar_m2p->p_resetn(this->p_resetn); + xbar_m2p->p_global_out(p_m2p_out); + xbar_m2p->p_global_in(p_m2p_in); + xbar_m2p->p_local_in[0](signal_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_m2p->p_local_out[p](signal_dspin_m2p_proc[p]); + + std::cout << " - M2P Coherence crossbar connected" << std::endl; + + ////////////////////////// P2M DSPIN local crossbar coherence + xbar_p2m->p_clk(this->p_clk); + xbar_p2m->p_resetn(this->p_resetn); + xbar_p2m->p_global_out(p_p2m_out); + xbar_p2m->p_global_in(p_p2m_in); + xbar_p2m->p_local_out[0](signal_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_p2m->p_local_in[p](signal_dspin_p2m_proc[p]); + + std::cout << " - P2M Coherence crossbar connected" << std::endl; + + ////////////////////// CLACK DSPIN local crossbar coherence + xbar_cla->p_clk(this->p_clk); + xbar_cla->p_resetn(this->p_resetn); + xbar_cla->p_global_out(p_cla_out); + xbar_cla->p_global_in(p_cla_in); + xbar_cla->p_local_in[0](signal_dspin_clack_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_cla->p_local_out[p](signal_dspin_clack_proc[p]); + + std::cout << " - CLA Coherence crossbar connected" << std::endl; + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk(this->p_clk); + proc[p]->p_resetn(this->p_resetn); + proc[p]->p_vci(signal_vci_ini_proc[p]); + proc[p]->p_dspin_m2p(signal_dspin_m2p_proc[p]); + proc[p]->p_dspin_p2m(signal_dspin_p2m_proc[p]); + proc[p]->p_dspin_clack(signal_dspin_clack_proc[p]); + + for ( size_t j = 0 ; j < 6 ; j++) + { + if ( j < 4 ) proc[p]->p_irq[j](signal_proc_irq[4*p + j]); + else proc[p]->p_irq[j](signal_false); + } + } + + std::cout << " - Processors connected" << std::endl; + + ///////////////////////////////////// XICU + xicu->p_clk(this->p_clk); + xicu->p_resetn(this->p_resetn); + xicu->p_vci(signal_vci_tgt_xicu); + + for (size_t i = 0 ; i < 16 ; i++) + { + xicu->p_irq[i](signal_proc_irq[i]); + } + + for (size_t i = 0; i < 16; i++) + { + if (i == 8) xicu->p_hwi[i] (signal_irq_memc); + else if (i == 9) xicu->p_hwi[i] (signal_irq_bdev); + else if (i == 10) xicu->p_hwi[i] (signal_irq_mtty); + else xicu->p_hwi[i] (signal_false); + } + + std::cout << " - XICU connected" << std::endl; + + // MEMC + memc->p_clk(this->p_clk); + memc->p_resetn(this->p_resetn); + memc->p_irq(signal_irq_memc); + memc->p_vci_ixr(signal_vci_xram); + memc->p_vci_tgt(signal_vci_tgt_memc); + memc->p_dspin_p2m(signal_dspin_p2m_memc); + memc->p_dspin_m2p(signal_dspin_m2p_memc); + memc->p_dspin_clack(signal_dspin_clack_memc); + + std::cout << " - MEMC connected" << std::endl; + + // XRAM + xram->p_clk(this->p_clk); + xram->p_resetn(this->p_resetn); + xram->p_vci(signal_vci_xram); + + std::cout << " - XRAM connected" << std::endl; + + // BDEV + bdev->p_clk(this->p_clk); + bdev->p_resetn(this->p_resetn); + bdev->p_irq(signal_irq_bdev); + bdev->p_vci_target(signal_vci_tgt_bdev); + bdev->p_vci_initiator(signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // MTTY (single channel) + mtty->p_clk(this->p_clk); + mtty->p_resetn(this->p_resetn); + mtty->p_vci(signal_vci_tgt_mtty); + mtty->p_irq[0](signal_irq_mtty); + + std::cout << " - MTTY connected" << std::endl; + + // XROM + xrom->p_clk(this->p_clk); + xrom->p_resetn(this->p_resetn); + xrom->p_vci(signal_vci_tgt_xrom); + + std::cout << " - XROM connected" << std::endl; +} // end constructor + +template + TsarFpgaCluster::~TsarFpgaCluster() +{ + for (size_t p = 0; p < m_nprocs ; p++) + { + if ( proc[p] ) delete proc[p]; + } + + delete memc; + delete xram; + delete xicu; + delete xbar_cmd; + delete xbar_m2p; + delete xbar_p2m; + delete xbar_cla; + delete wi_gate; + delete wt_gate; + delete bdev; + delete mtty; + delete xrom; +} + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + + +