Changeset 96

Timestamp:

Sep 21, 2010, 8:01:32 PM (14 years ago)

Author:

gao

Message:

Redo ins TLB access bit update when it miss in dcache

File:

• trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp (modified) (1 diff)

trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp

@@ -2293 +2293 @@
         else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
         {
-            r_dcache_itlb_ll_acc_req = true;
-            r_dcache_fsm = DCACHE_ITLB_LL_WAIT;         
-            m_cpt_dcache_data_write++;      
+            data_t rsp_itlb_miss;
+            bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+            if ( itlb_hit_dcache )
+            {
+                r_dcache_itlb_ll_acc_req = true;
+                r_dcache_fsm = DCACHE_ITLB_LL_WAIT;             
+                m_cpt_dcache_data_write++;          
+            }
+            else
+            {
+                r_itlb_acc_dcache_req = false;
+                r_itlb_acc_redo_req = true;
+                r_dcache_fsm = DCACHE_IDLE;
+            }    
         }
         else if (dreq.valid)