Ignore:
Timestamp:
Apr 6, 2015, 10:29:14 AM (10 years ago)
Author:
cfuguet
Message:

bugfix:tsar_boot: cache aligned structures should use the
CACHE_LINE_SIZE constant

  • Define a macro for the cache aligned attribute.
Location:
trunk/softs/tsar_boot/drivers
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/softs/tsar_boot/drivers/reset_bdv.c

    r962 r968  
    5050
    5151////////////////////////////////////
    52 int reset_bdv_read( unsigned int lba,
    53                     void* buffer,
    54                     unsigned int count )
     52int reset_bdv_read( unsigned int lba, void* buffer, unsigned int count )
    5553{
    5654    // block_device configuration
    57     iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], (unsigned int) buffer );
     55    iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], (unsigned int)buffer );
    5856    iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], count );
    5957    iowrite32( &ioc_address[BLOCK_DEVICE_LBA], lba );
    … …  
    6159
    6260    //  trigger transfer
    63     iowrite32( &ioc_address[BLOCK_DEVICE_OP], ( unsigned int )
    64                BLOCK_DEVICE_READ );
     61    iowrite32( &ioc_address[BLOCK_DEVICE_OP],
     62               (unsigned int)BLOCK_DEVICE_READ );
    6563
    6664#if (RESET_HARD_CC == 0) || USE_IOB
    … …  
    8280            break;
    8381        }
    84         if ( status == BLOCK_DEVICE_READ_ERROR   )
     82        if ( status == BLOCK_DEVICE_READ_ERROR )
    8583        {
    8684            reset_puts("ERROR during read on the BLK device\n");

  • trunk/softs/tsar_boot/drivers/reset_hba.c

    r964 r968  
    99#include <reset_tty.h>
    1010#include <reset_inval.h>
     11#include <reset_utils.h>
    1112#include <io.h>
    1213#include <defs.h>
    … …  
    1718
    1819// command descriptor (one single command)
    19 static hba_cmd_desc_t  hba_cmd_desc  __attribute__((aligned(64)));
     20static hba_cmd_desc_t hba_cmd_desc __cache_aligned__;
    2021
    2122// command table (one single command)
    22 static hba_cmd_table_t  hba_cmd_table __attribute__((aligned(64)));
     23static hba_cmd_table_t hba_cmd_table __cache_aligned__;
    2324
    2425// IOC/HBA device base address
    … …  
    3536// return 0 if success, -1 if error
    3637///////////////////////////////////////////////////////////////////////////////
    37 int reset_hba_read( unsigned int lba, 
     38int reset_hba_read( unsigned int lba,
    3839                    void*        buffer,
    39                     unsigned int count )   
     40                    unsigned int count )
    4041{
    4142    unsigned int       pxci;           // HBA_PXCI register value
    … …  
    4647    {
    4748        reset_puts("\n[RESET ERROR] in reset_hba_read() ");
    48         reset_puts("buffer not aligned on 64 bytes: base = "); 
     49        reset_puts("buffer not aligned on 64 bytes: base = ");
    4950        reset_putx( (unsigned int)buffer );
    50         reset_puts("\n"); 
     51        reset_puts("\n");
    5152        return -1;
    5253    }
    … …  
    6970    hba_cmd_desc.prdtl[1] = 0;
    7071    hba_cmd_desc.flag[0]  = 0;  // read
    71    
     72
    7273#if USE_IOB
    7374    // update external memory for command table
    … …  
    9697        pxci = ioread32( &ioc_address[HBA_PXCI] );
    9798    }
    98     while( pxci ); 
    99              
     99    while( pxci );
     100
    100101    // get PXIS register
    101102    pxis = ioread32( &ioc_address[HBA_PXIS] );
    … …  
    107108    iowrite32( &ioc_address[HBA_PXCI] , 0 );
    108109
    109     // check error status 
    110     if ( pxis & 0x40000000 ) 
     110    // check error status
     111    if ( pxis & 0x40000000 )
    111112    {
    112113        reset_puts("[RESET ERROR] in reset_hba_read() : "
    … …  
    120121
    121122///////////////////////////////////////////////////////////////////////////////
    122 // This function initialises both the HBA registers and the 
     123// This function initialises both the HBA registers and the
    123124// memory structures used by the AHCI peripheral (one single command).
    124125///////////////////////////////////////////////////////////////////////////////
    … …  
    126127{
    127128    // initialise the command descriptor
    128     hba_cmd_desc.ctba  = (unsigned int)&hba_cmd_table;
     129    hba_cmd_desc.ctba = (unsigned int)&hba_cmd_table;
    129130    hba_cmd_desc.ctbau = 0;
    130131
    131132#if USE_IOB
    132133    // update external memory for the commande descriptor
    133     reset_L2_sync( &hba_cmd_desc , sizeof( hba_cmd_desc_t ) );
     134    reset_L2_sync(&hba_cmd_desc , sizeof( hba_cmd_desc_t ) );
    134135#endif
    135     // initialise HBA registers 
    136     iowrite32( &ioc_address[HBA_PXCLB]  , (unsigned int)&hba_cmd_desc );
    137     iowrite32( &ioc_address[HBA_PXCLBU] , 0 );
    138     iowrite32( &ioc_address[HBA_PXIE]   , 0 );
    139     iowrite32( &ioc_address[HBA_PXIS]   , 0 );
    140     iowrite32( &ioc_address[HBA_PXCI]   , 0 );
    141     iowrite32( &ioc_address[HBA_PXCMD]  , 1 );
     136    // initialise HBA registers
     137    iowrite32(&ioc_address[HBA_PXCLB], (unsigned int)&hba_cmd_desc );
     138    iowrite32(&ioc_address[HBA_PXCLBU], 0 );
     139    iowrite32(&ioc_address[HBA_PXIE], 0 );
     140    iowrite32(&ioc_address[HBA_PXIS], 0 );
     141    iowrite32(&ioc_address[HBA_PXCI], 0 );
     142    iowrite32(&ioc_address[HBA_PXCMD], 1 );
    142143
    143144    return 0;
    144145}
    145 
    146146
    147147// Local Variables:
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