Index: /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 95)
+++ /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 96)
@@ -2293,7 +2293,18 @@
     	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
     	{
-            r_dcache_itlb_ll_acc_req = true;
-	    r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    	
-            m_cpt_dcache_data_write++;	    
+	    data_t rsp_itlb_miss;
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+	    if ( itlb_hit_dcache )
+	    {
+                r_dcache_itlb_ll_acc_req = true;
+	        r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    	
+                m_cpt_dcache_data_write++;	    
+	    }
+	    else
+	    {
+		r_itlb_acc_dcache_req = false;
+		r_itlb_acc_redo_req = true;
+		r_dcache_fsm = DCACHE_IDLE;
+	    }    
     	}
         else if (dreq.valid)