Index: trunk/platforms/tsar_generic_iob/arch.py =================================================================== --- trunk/platforms/tsar_generic_iob/arch.py (revision 971) +++ trunk/platforms/tsar_generic_iob/arch.py (revision 972) @@ -19,5 +19,5 @@ # # All clusters contain (nb_procs) processors, one L2 cache, one XCU, and -# one DMA controller. +# one optional hardware coprocessor connected to a MWMR_DMA controller. # # The "constructor" parameters (defined in Makefile) are: @@ -27,7 +27,8 @@ # - nb_ttys : number of TTY channels # - fbf_width : frame_buffer width = frame_buffer heigth -# - ioc_type : can be 'BDV','HBA','SDC', but not 'RDK' -# -# The other hardware parameters (defined below) are: +# - ioc_type : can be 'BDV','HBA','SDC', but not 'RDK' +# +# +# The other hardware parameters (defined in this script) are: # - nb_nics : number of NIC channels # - nb_cmas : number of CMA channels @@ -40,4 +41,6 @@ # - use_ramdisk : use a ramdisk when True # - vseg_increment : address increment for replicated vsegs +# - mwr_type : coprocessor type / can be 'GCD','DCT','NOPE' +# - use_dma : one single channel DMA per cluster if non zero # # Regarding the boot and kernel vsegs mapping : @@ -59,5 +62,5 @@ nb_ttys = 1, fbf_width = 128, - ioc_type = 'BDV' ): + ioc_type = 'HBA' ): ### define architecture constants @@ -71,8 +74,9 @@ p_width = 4 paddr_width = 40 - irq_per_proc = 4 # NetBSD constraint + irq_per_proc = 4 peri_increment = 0x10000 - - ### parameters checking + mwr_type = 'CPY' + + ### constructor parameters checking assert( nb_procs <= (1 << p_width) ) @@ -90,4 +94,6 @@ assert( ioc_type in [ 'BDV' , 'HBA' , 'SDC' ] ) + + assert( mwr_type in [ 'GCD' , 'DCT' , 'CPY' , 'NONE' ] ) ### define platform name @@ -104,6 +110,6 @@ xcu_size = 0x1000 # 4 Kbytes - dma_base = 0x00B1000000 - dma_size = 0x1000 # 4 Kbytes + mwr_base = 0x00B1000000 + mwr_size = 0x1000 # 4 Kbytes mmc_base = 0x00B2000000 @@ -207,13 +213,6 @@ ### components replicated in all clusters - ram = mapping.addRam( 'RAM', base = ram_base + offset, + mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) - - mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, - size = mmc_size, ptype = 'MMC' ) - - dma = mapping.addPeriph( 'DMA', base = dma_base + offset, - size = dma_size, ptype = 'DMA', - channels = nb_procs ) xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, @@ -223,11 +222,26 @@ mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) - - for i in xrange ( dma.channels ): - mapping.addIrq( xcu, index = 1+i, isrtype = 'ISR_DMA', - channel = i ) + mapping.addIrq( xcu, index = 1, isrtype = 'ISR_MWR' ) + + mapping.addPeriph( 'MMC', base = mmc_base + offset, + size = mmc_size, ptype = 'MMC' ) + + if ( mwr_type == 'GCD' ): + mapping.addPeriph( 'MWR', base = mwr_base + offset, + size = mwr_size, ptype = 'MWR', subtype = 'GCD', + arg0 = 2, arg1 = 1, arg2 = 1, arg3 = 0 ) + + if ( mwr_type == 'DCT' ): + mapping.addPeriph( 'MWR', base = mwr_base + offset, + size = mwr_size, ptype = 'MWR', subtype = 'DCT', + arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 ) + + if ( mwr_type == 'CPY' ): + mapping.addPeriph( 'MWR', base = mwr_base + offset, + size = mwr_size, ptype = 'MWR', subtype = 'CPY', + arg0 = 1, arg1 = 1, arg2 = 1, arg3 = 0 ) for p in xrange ( nb_procs ): - mapping.addProc( x, y, p ) + mapping.addProc( x , y , p ) ### external peripherals in cluster_io @@ -406,11 +420,12 @@ local = False, big = False ) - mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size, - '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA', - local = False, big = False ) - mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC', local = False, big = False ) + + if ( mwr_type != 'NONE' ): + mapping.addGlobal( 'seg_mwr_%d_%d' %(x,y), mwr_base + offset, mwr_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MWR', + local = False, big = False ) return mapping Index: trunk/platforms/tsar_generic_iob/top.cpp =================================================================== --- trunk/platforms/tsar_generic_iob/top.cpp (revision 971) +++ trunk/platforms/tsar_generic_iob/top.cpp (revision 972) @@ -48,13 +48,14 @@ // - IOPIC HWI[31:16] connected to IRQ_TTY_RX[15:0] // -// Besides the external peripherals, each cluster contains one XICU component, -// and one multi channels DMA component. -// The XICU component is mainly used to handle WTI IRQs, as only -// 1 + NB_PROCS_MAX HWI IRQs are connected to XICU in each cluster: +// Each cluster contains the following component: +// - From 1 to 8 MIP32 processors +// - One L2 cache controller +// - One XICU component, +// - One - optional - single channel DMA controler, +// - One - optional - hardware coprocessor +// The XICU component is mainly used to handle WTI IRQs, as at most +// 2 HWI IRQs are connected to XICU in each cluster: // - IRQ_IN[0] : MMC -// - IRQ_IN[1] : DMA channel 0 -// - IRQ_IN[2] : DMA channel 1 -// - ... ... -// - IRQ_IN[NB_PROCS_MAX] : DMA channel NB_PROCS_MAX +// - IRQ_IN[1] : MWR // // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) @@ -131,4 +132,6 @@ #include "mapping_table.h" + + #include "tsar_iob_cluster.h" #include "vci_chbuf_dma.h" @@ -144,7 +147,17 @@ #include "alloc_elems.h" -/////////////////////////////////////////////////// -// OS -/////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////// +// Coprocessor type (must be replicated in tsar_iob_cluster) +////////////////////////////////////////////////////////////////// + +#define MWR_COPROC_CPY 0 +#define MWR_COPROC_DCT 1 +#define MWR_COPROC_GCD 2 + +////////////////////////////////////////////////////////////////// +// For ALMOS +////////////////////////////////////////////////////////////////// + #define USE_ALMOS 0 @@ -153,7 +166,7 @@ #define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" -/////////////////////////////////////////////////// -// Parallelisation -/////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// +// Parallelisation +////////////////////////////////////////////////////////////////// #define USING_OPENMP 0 @@ -163,7 +176,7 @@ #endif -/////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// // DSPIN parameters -/////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// #define dspin_int_cmd_width 39 @@ -173,7 +186,7 @@ #define dspin_ram_rsp_width 64 -/////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// // VCI fields width for the 3 VCI networks -/////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////// #define vci_cell_width_int 4 @@ -214,4 +227,9 @@ #define L1_DSETS 64 +#if BOOT_DEBUG_ELF +_printf("\n[DEBUG BOOT_ELF] P[%d,%d,%d] copy segment %d :\n" + " vaddr = %x / size = %x / paddr = %l\n", + x , y , p , seg_id , seg_vaddr , seg_memsz , seg_paddr ); +#endif #define DISK_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" @@ -249,5 +267,5 @@ // Two different initiators cannot have the same SRCID, but a given // initiator can have two alias SRCIDs: -// - Internal initiators (procs, mdma) are replicated in all clusters, +// - Internal initiators (procs, mwmr) are replicated in all clusters, // and each initiator has one single SRCID. // - External initiators (disk, cdma) are not replicated, but can be @@ -263,5 +281,5 @@ #define PROC_LOCAL_SRCID 0x0 // from 0 to 7 -#define MDMA_LOCAL_SRCID 0x8 +#define MWMR_LOCAL_SRCID 0x8 #define IOBX_LOCAL_SRCID 0x9 #define MEMC_LOCAL_SRCID 0xA @@ -276,9 +294,9 @@ #define INT_MEMC_TGT_ID 0 #define INT_XICU_TGT_ID 1 -#define INT_MDMA_TGT_ID 2 +#define INT_MWMR_TGT_ID 2 #define INT_IOBX_TGT_ID 3 #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) -#define INT_MDMA_INI_ID (NB_PROCS_MAX) +#define INT_MWMR_INI_ID (NB_PROCS_MAX) #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) @@ -439,38 +457,41 @@ // checking hardware parameters assert( (XMAX <= 16) and - "The XMAX parameter cannot be larger than 16" ); + "Error in tsar_generic_iob : XMAX parameter cannot be larger than 16" ); assert( (YMAX <= 16) and - "The YMAX parameter cannot be larger than 16" ); + "Error in tsar_generic_iob : YMAX parameter cannot be larger than 16" ); assert( (NB_PROCS_MAX <= 8) and - "NB_PROCS_MAX parameter cannot be larger than 8" ); + "Error in tsar_generic_iob : NB_PROCS_MAX parameter cannot be larger than 8" ); assert( (XCU_NB_HWI > NB_PROCS_MAX) and - "XCU_NB_HWI must be larger than NB_PROCS_MAX" ); + "Error in tsar_generic_iob : XCU_NB_HWI must be larger than NB_PROCS_MAX" ); assert( (XCU_NB_PTI >= NB_PROCS_MAX) and - "XCU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); + "Error in tsar_generic_iob : XCU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); assert( (XCU_NB_WTI >= 4*NB_PROCS_MAX) and - "XCU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); + "Error in tsar_generic_iob : XCU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); assert( (XCU_NB_OUT >= 4*NB_PROCS_MAX) and - "XCU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); + "Error in tsar_generic_iob : XCU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); - assert( (NB_DMA_CHANNELS >= NB_PROCS_MAX) and - "The NB_DMA_CHANNELS parameter cannot be larger than 8" ); - assert( (NB_TTY_CHANNELS >= 1) and (NB_TTY_CHANNELS <= 16) and - "The NB_TTY_CHANNELS parameter cannot be larger than 16" ); + "Error in tsar_generic_iob : NB_TTY_CHANNELS parameter cannot be larger than 16" ); assert( (NB_NIC_CHANNELS <= 2) and - "The NB_NIC_CHANNELS parameter cannot be larger than 2" ); + "Error in tsar_generic_iob : NB_NIC_CHANNELS parameter cannot be larger than 2" ); assert( (NB_CMA_CHANNELS <= 4) and - "The NB_CMA_CHANNELS parameter cannot be larger than 4" ); + "Error in tsar_generic_iob : NB_CMA_CHANNELS parameter cannot be larger than 4" ); assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and - "You must have X_WIDTH == Y_WIDTH == 4"); + "Error in tsar_generic_iob : You must have X_WIDTH == Y_WIDTH == 4"); + + assert( ((USE_MWR_CPY + USE_MWR_GCD + USE_MWR_DCT) == 1) and + "Error in tsar_generic_iob : No MWR coprocessor found in hard_config.h"); + + assert( ((USE_IOC_HBA + USE_IOC_BDV + USE_IOC_SDC) == 1) and + "Error in tsar_generic_iob : NoIOC controller found in hard_config.h"); std::cout << std::endl << std::dec @@ -478,5 +499,4 @@ << " - YMAX = " << YMAX << std::endl << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl - << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl @@ -492,4 +512,5 @@ << " - DEBUG_PROCID = " << debug_proc_id << std::endl << " - DEBUG_MEMCID = " << debug_memc_id << std::endl + << " - DEBUG_XRAMID = " << debug_xram_id << std::endl << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; @@ -529,6 +550,6 @@ // - two levels address decoding for commands // - two levels srcid decoding for responses - // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster - // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster + // - NB_PROCS_MAX + 2 (MWMR, IOBX) local initiators per cluster + // - 4 local targets (MEMC, XICU, MWMR, IOBX) per cluster ///////////////////////////////////////////////////////////////////// MappingTable maptab_int( vci_address_width, @@ -563,8 +584,8 @@ IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); - std::ostringstream smdma; - smdma << "int_seg_mdma_" << x << "_" << y; - maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, - IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); + std::ostringstream smwmr; + smwmr << "int_seg_mwmr_" << x << "_" << y; + maptab_int.add(Segment(smwmr.str(), SEG_MWR_BASE+offset, SEG_MWR_SIZE, + IntTab(cluster(x,y), INT_MWMR_TGT_ID), not cacheable)); // the following segments are only defined in cluster_iob0 or in cluster_iob1 @@ -616,6 +637,6 @@ // and the port index on the local interconnect. - maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), - IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); + maptab_int.srcid_map( IntTab( cluster(x,y), MWMR_LOCAL_SRCID ), + IntTab( cluster(x,y), INT_MWMR_INI_ID ) ); maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), @@ -1022,4 +1043,9 @@ dspin_ram_rsp_width>* clusters[XMAX][YMAX]; + unsigned int coproc_type; + if ( USE_MWR_CPY ) coproc_type = MWR_COPROC_CPY; + if ( USE_MWR_DCT ) coproc_type = MWR_COPROC_DCT; + if ( USE_MWR_GCD ) coproc_type = MWR_COPROC_GCD; + #if USING_OPENMP #pragma omp parallel @@ -1050,4 +1076,5 @@ IOX_IOB0_TGT_ID : IOX_IOB1_TGT_ID ; + std::ostringstream sc; @@ -1062,5 +1089,4 @@ sc.str().c_str(), NB_PROCS_MAX, - NB_DMA_CHANNELS, x, y, @@ -1079,9 +1105,9 @@ INT_MEMC_TGT_ID, INT_XICU_TGT_ID, - INT_MDMA_TGT_ID, + INT_MWMR_TGT_ID, INT_IOBX_TGT_ID, INT_PROC_INI_ID, - INT_MDMA_INI_ID, + INT_MWMR_INI_ID, INT_IOBX_INI_ID, @@ -1106,4 +1132,6 @@ XCU_NB_WTI, XCU_NB_OUT, + + coproc_type, loader, @@ -1501,11 +1529,15 @@ clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); -// clusters[x][y]->mdma->print_trace(); -// std::ostringstream mdma_tgt_signame; -// mdma_tgt_signame << "[SIG]MDMA_TGT_" << x << "_" << y; -// clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_tgt_signame.str()); -// std::ostringstream mdma_ini_signame; -// mdma_ini_signame << "[SIG]MDMA_INI_" << x << "_" << y; -// clusters[x][y]->signal_int_vci_ini_mdma.print_trace(mdma_ini_signame.str()); + // coprocessor in cluster(x,y) + clusters[x][y]->mwmr->print_trace(); + std::ostringstream mwmr_tgt_signame; + mwmr_tgt_signame << "[SIG]MWMR_TGT_" << x << "_" << y; + clusters[x][y]->signal_int_vci_tgt_mwmr.print_trace(mwmr_tgt_signame.str()); + std::ostringstream mwmr_ini_signame; + mwmr_ini_signame << "[SIG]MWMR_INI_" << x << "_" << y; + clusters[x][y]->signal_int_vci_ini_mwmr.print_trace(mwmr_ini_signame.str()); + if ( USE_MWR_CPY ) clusters[x][y]->cpy->print_trace(); + if ( USE_MWR_DCT ) clusters[x][y]->dct->print_trace(); + if ( USE_MWR_GCD ) clusters[x][y]->gcd->print_trace(); // local interrupts in cluster(x,y) @@ -1514,10 +1546,7 @@ << " ACTIVE" << std::endl; - for ( size_t c = 0 ; c < NB_DMA_CHANNELS ; c++ ) - { - if( clusters[x][y]->signal_irq_mdma[c].read() ) - std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << c - << " ACTIVE" << std::endl; - } + if( clusters[x][y]->signal_irq_mwmr.read() ) + std::cout << "### IRQ_MWR_" << std::dec << x << "_" << y + << " ACTIVE" << std::endl; for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 971) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 972) @@ -29,4 +29,5 @@ Uses('common:iss2'), Uses('common:elf_file_loader'), + Uses('caba:coproc_signals'), # internal network components @@ -47,6 +48,10 @@ cell_size = parameter.Reference('vci_data_width_int')), - Uses('caba:vci_multi_dma', + Uses('caba:vci_mwmr_dma', cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:coproc_gcd'), + Uses('caba:coproc_dct'), + Uses('caba:coproc_cpy'), Uses('caba:vci_local_crossbar', Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 971) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 972) @@ -28,8 +28,12 @@ #include "dspin_router.h" #include "virtual_dspin_router.h" -#include "vci_multi_dma.h" +#include "vci_mwmr_dma.h" #include "vci_mem_cache.h" #include "vci_cc_vcache_wrapper.h" #include "vci_io_bridge.h" +#include "coproc_signals.h" +#include "coproc_gcd.h" +#include "coproc_dct.h" +#include "coproc_cpy.h" namespace soclib { namespace caba { @@ -71,7 +75,13 @@ sc_signal signal_false; sc_signal signal_proc_it[32]; - sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mwmr; sc_signal signal_irq_memc; + // Coprocessor signals + CoprocSignals signal_to_coproc[8]; + CoprocSignals signal_from_coproc[8]; + sc_signal signal_config_coproc[8]; + sc_signal signal_status_coproc[8]; + // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars DspinSignals signal_int_dspin_cmd_l2g_d; @@ -88,10 +98,10 @@ // INT network VCI signals between VCI components and VCI local crossbar VciSignals signal_int_vci_ini_proc[8]; - VciSignals signal_int_vci_ini_mdma; + VciSignals signal_int_vci_ini_mwmr; VciSignals signal_int_vci_ini_iobx; VciSignals signal_int_vci_tgt_memc; VciSignals signal_int_vci_tgt_xicu; - VciSignals signal_int_vci_tgt_mdma; + VciSignals signal_int_vci_tgt_mwmr; VciSignals signal_int_vci_tgt_iobx; @@ -144,5 +154,9 @@ VciXicu* xicu; - VciMultiDma* mdma; + VciMwmrDma* mwmr; + + CoprocGcd* gcd; + CoprocDct* dct; + CoprocCpy* cpy; VciLocalCrossbar* int_xbar_d; @@ -188,5 +202,4 @@ TsarIobCluster( sc_module_name insname, size_t nb_procs, - size_t nb_dmas, size_t x, // x coordinate size_t y, // y coordinate @@ -205,8 +218,8 @@ size_t int_memc_tgt_id, size_t int_xicu_tgt_id, - size_t int_mdma_tgt_id, + size_t int_mwmr_tgt_id, size_t int_iobx_tgt_id, size_t int_proc_ini_id, - size_t int_mdma_ini_id, + size_t int_mwmr_ini_id, size_t int_iobx_ini_id, @@ -231,4 +244,6 @@ size_t xcu_nb_irq, + size_t coproc_type, + const Loader &loader, // loader for XRAM @@ -245,5 +260,4 @@ void init(); - }; Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 971) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 972) @@ -15,4 +15,8 @@ #include "../include/tsar_iob_cluster.h" +#define MWR_COPROC_CPY 0 +#define MWR_COPROC_DCT 1 +#define MWR_COPROC_GCD 2 + #define tmpl(x) \ template( - s_mdma.str().c_str(), + //////////// MWMR controller and coprocessor + std::ostringstream s_mwmr; + std::ostringstream s_copro; + s_mwmr << "mwmr_" << x_id << "_" << y_id; + + if ( coproc_type == MWR_COPROC_CPY) + { + s_copro << "cpy_" << x_id << "_" << y_id; + cpy = new CoprocCpy( s_copro.str().c_str(), 64 ); // burst size + + mwmr = new VciMwmrDma( + s_mwmr.str().c_str(), mt_int, - IntTab(cluster_id, nb_procs), // SRCID - IntTab(cluster_id, int_mdma_tgt_id), // TGTID - 64, // burst size - nb_dmas); // number of IRQs + IntTab(cluster_id, int_mwmr_ini_id), // SRCID + IntTab(cluster_id, int_mwmr_tgt_id), // TGTID + 1, // nb to_coproc ports + 1, // nb from_coproc ports + 1, // nb config registers + 0, // nb status registers + 64 ); // burst size (bytes) + } + if ( coproc_type == MWR_COPROC_DCT ) + { + s_copro << "dct_" << x_id << "_" << y_id; + dct = new CoprocDct( s_copro.str().c_str(), 64 , 16 ); // burst size / latency + + mwmr = new VciMwmrDma( + s_mwmr.str().c_str(), + mt_int, + IntTab(cluster_id, int_mwmr_ini_id), // SRCID + IntTab(cluster_id, int_mwmr_tgt_id), // TGTID + 1, // nb to_coproc ports + 1, // nb from_coproc ports + 1, // nb config registers + 0, // nb status registers + 64 ); // burst size (bytes) + } + if ( coproc_type == MWR_COPROC_GCD ) + { + s_copro << "gcd_" << x_id << "_" << y_id; + gcd = new CoprocGcd( s_copro.str().c_str(), 64 ); // burst size + + mwmr = new VciMwmrDma( + s_mwmr.str().c_str(), + mt_int, + IntTab(cluster_id, int_mwmr_ini_id), // SRCID + IntTab(cluster_id, int_mwmr_tgt_id), // TGTID + 2, // nb to_coproc ports + 1, // nb from_coproc ports + 1, // nb config registers + 0, // nb status registers + 64 ); // burst size (bytes) + } /////////// Direct LOCAL_XBAR(S) @@ -435,6 +482,6 @@ int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); - int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); - int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); + int_xbar_d->p_to_target[int_mwmr_tgt_id] (signal_int_vci_tgt_mwmr); + int_xbar_d->p_to_initiator[int_mwmr_ini_id] (signal_int_vci_ini_mwmr); for (size_t p = 0; p < nb_procs; p++) int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); @@ -513,5 +560,5 @@ { if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); - else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); + else if ( i == 1 ) xicu->p_hwi[i] (signal_irq_mwmr); else xicu->p_hwi[i] (signal_false); } @@ -546,11 +593,62 @@ xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); - /////////////////////////////////// MDMA - mdma->p_clk (this->p_clk); - mdma->p_resetn (this->p_resetn); - mdma->p_vci_target (signal_int_vci_tgt_mdma); - mdma->p_vci_initiator (signal_int_vci_ini_mdma); - for (size_t i=0 ; ip_irq[i] (signal_irq_mdma[i]); + /////////////////////////////////// GCD coprocessor + if ( coproc_type == MWR_COPROC_GCD ) + { + gcd->p_clk (this->p_clk); + gcd->p_resetn (this->p_resetn); + gcd->p_opa (signal_to_coproc[0]); + gcd->p_opb (signal_to_coproc[1]); + gcd->p_res (signal_from_coproc[0]); + gcd->p_config (signal_config_coproc[0]); + + mwmr->p_clk (this->p_clk); + mwmr->p_resetn (this->p_resetn); + mwmr->p_vci_target (signal_int_vci_tgt_mwmr); + mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); + mwmr->p_to_coproc[0] (signal_to_coproc[0]); + mwmr->p_to_coproc[1] (signal_to_coproc[1]); + mwmr->p_from_coproc[0] (signal_from_coproc[0]); + mwmr->p_config[0] (signal_config_coproc[0]); + mwmr->p_irq (signal_irq_mwmr); + } + + /////////////////////////////////// DCT coprocessor + if ( coproc_type == MWR_COPROC_DCT ) + { + dct->p_clk (this->p_clk); + dct->p_resetn (this->p_resetn); + dct->p_in (signal_to_coproc[0]); + dct->p_out (signal_from_coproc[0]); + dct->p_config (signal_config_coproc[0]); + + mwmr->p_clk (this->p_clk); + mwmr->p_resetn (this->p_resetn); + mwmr->p_vci_target (signal_int_vci_tgt_mwmr); + mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); + mwmr->p_to_coproc[0] (signal_to_coproc[0]); + mwmr->p_from_coproc[0] (signal_from_coproc[0]); + mwmr->p_config[0] (signal_config_coproc[0]); + mwmr->p_irq (signal_irq_mwmr); + } + + /////////////////////////////////// CPY coprocessor + if ( coproc_type == MWR_COPROC_CPY ) + { + cpy->p_clk (this->p_clk); + cpy->p_resetn (this->p_resetn); + cpy->p_load (signal_to_coproc[0]); + cpy->p_store (signal_from_coproc[0]); + cpy->p_config (signal_config_coproc[0]); + + mwmr->p_clk (this->p_clk); + mwmr->p_resetn (this->p_resetn); + mwmr->p_vci_target (signal_int_vci_tgt_mwmr); + mwmr->p_vci_initiator (signal_int_vci_ini_mwmr); + mwmr->p_to_coproc[0] (signal_to_coproc[0]); + mwmr->p_from_coproc[0] (signal_from_coproc[0]); + mwmr->p_config[0] (signal_config_coproc[0]); + mwmr->p_irq (signal_irq_mwmr); + } //////////////////////////// RAM network CMD & RSP routers @@ -624,5 +722,5 @@ signal_ram_dspin_cmd_false.write = false; signal_ram_dspin_rsp_false.read = true; -} // end init +} }}