Changeset 977 for branches/reconfiguration/modules
- Timestamp:
- Apr 15, 2015, 4:02:12 PM (10 years ago)
- Location:
- branches/reconfiguration/modules/dspin_local_crossbar/caba/source
- Files:
-
- 2 edited
-
include/dspin_local_crossbar.h (modified) (6 diffs)
-
src/dspin_local_crossbar.cpp (modified) (29 diffs)
Legend:
- Unmodified
- Added
- Removed
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branches/reconfiguration/modules/dspin_local_crossbar/caba/source/include/dspin_local_crossbar.h
r976 r977 5 5 * 6 6 * SOCLIB_LGPL_HEADER_BEGIN 7 * 7 * 8 8 * This file is part of SoCLib, GNU LGPLv2.1. 9 * 9 * 10 10 * SoCLib is free software; you can redistribute it and/or modify it 11 11 * under the terms of the GNU Lesser General Public License as published 12 12 * by the Free Software Foundation; version 2.1 of the License. 13 * 13 * 14 14 * SoCLib is distributed in the hope that it will be useful, but 15 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 17 * Lesser General Public License for more details. 18 * 18 * 19 19 * You should have received a copy of the GNU Lesser General Public 20 20 * License along with SoCLib; if not, write to the Free Software 21 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 22 22 * 02110-1301 USA 23 * 23 * 24 24 * SOCLIB_LGPL_HEADER_END 25 25 * … … 44 44 45 45 template<size_t flit_width> 46 47 48 46 class DspinLocalCrossbar 47 : public soclib::caba::BaseModule 48 { 49 49 // Input Port FSM 50 enum 50 enum 51 51 { 52 52 INFSM_IDLE, … … 57 57 }; 58 58 59 60 59 protected: 60 SC_HAS_PROCESS(DspinLocalCrossbar); 61 61 62 62 public: 63 63 64 65 66 67 DspinInput<flit_width>p_global_in;68 DspinOutput<flit_width>p_global_out;69 DspinInput<flit_width>*p_local_in;70 DspinOutput<flit_width>*p_local_out;64 // ports 65 sc_in<bool> p_clk; 66 sc_in<bool> p_resetn; 67 DspinInput<flit_width> p_global_in; 68 DspinOutput<flit_width> p_global_out; 69 DspinInput<flit_width>* p_local_in; 70 DspinOutput<flit_width>* p_local_out; 71 71 72 72 void print_trace(); 73 73 74 75 DspinLocalCrossbar( sc_module_name name, 74 // constructor / destructor 75 DspinLocalCrossbar( sc_module_name name, 76 76 const MappingTable &mt, 77 77 const size_t x, // cluster x coordinate 78 78 const size_t y, // cluster y coordinate 79 79 const size_t x_width, // x field width 80 const size_t y_width, // y field width 80 const size_t y_width, // y field width 81 81 const size_t l_width, // local field width 82 82 const size_t nb_local_inputs, … … 90 90 ~DspinLocalCrossbar(); 91 91 92 92 private: 93 93 94 94 // define the FIFO flit 95 typedef struct internal_flit_s 95 typedef struct internal_flit_s 96 96 { 97 97 sc_uint<flit_width> data; … … 99 99 } internal_flit_t; 100 100 101 102 sc_signal<bool>*r_alloc_out; // output port allocated103 101 // internal registers 102 sc_signal<bool> *r_alloc_out; // output port allocated 103 sc_signal<size_t> *r_index_out; // owner input port index 104 104 internal_flit_t *r_buf_in; // input port fifo extension 105 105 sc_signal<int> *r_fsm_in; // input port state 106 106 sc_signal<size_t> *r_index_in; // requested output port index 107 107 108 109 110 108 // fifos 109 soclib::caba::GenericFifo<internal_flit_t>* r_fifo_in; 110 soclib::caba::GenericFifo<internal_flit_t>* r_fifo_out; 111 111 112 113 114 115 116 117 118 119 120 121 122 123 112 // structural parameters 113 const size_t m_local_x; 114 const size_t m_local_y; 115 const size_t m_x_width; 116 const size_t m_x_shift; 117 const size_t m_x_mask; 118 const size_t m_y_width; 119 const size_t m_y_shift; 120 const size_t m_y_mask; 121 const size_t m_l_width; 122 const size_t m_l_shift; 123 const size_t m_l_mask; 124 124 const size_t m_local_inputs; 125 125 const size_t m_local_outputs; … … 133 133 AddressDecodingTable<uint32_t, size_t> m_rsp_rt; 134 134 135 // methods 136 137 135 // methods 136 void transition(); 137 void genMoore(); 138 138 size_t route( sc_uint<flit_width> data, size_t index ); 139 139 bool is_broadcast( sc_uint<flit_width> data ); 140 140 }; 141 141 142 142 }} // end namespace 143 143 144 144 #endif // DSPIN_LOCAL_CROSSBAR_H_ 145 145 -
branches/reconfiguration/modules/dspin_local_crossbar/caba/source/src/dspin_local_crossbar.cpp
r976 r977 6 6 * 7 7 * SOCLIB_LGPL_HEADER_BEGIN 8 * 8 * 9 9 * This file is part of SoCLib, GNU LGPLv2.1. 10 * 10 * 11 11 * SoCLib is free software; you can redistribute it and/or modify it 12 12 * under the terms of the GNU Lesser General Public License as published 13 13 * by the Free Software Foundation; version 2.1 of the License. 14 * 14 * 15 15 * SoCLib is distributed in the hope that it will be useful, but 16 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 18 * Lesser General Public License for more details. 19 * 19 * 20 20 * You should have received a copy of the GNU Lesser General Public 21 21 * License along with SoCLib; if not, write to the Free Software … … 39 39 // constructor 40 40 ////////////////////////////////////////////////////////// 41 tmpl(/**/)::DspinLocalCrossbar( sc_module_name name, 41 tmpl(/**/)::DspinLocalCrossbar( sc_module_name name, 42 42 const MappingTable &mt, 43 43 const size_t x, … … 123 123 r_fifo_in = (GenericFifo<internal_flit_t>*) 124 124 malloc(sizeof(GenericFifo<internal_flit_t>) * (m_local_inputs + 1)); 125 125 126 126 r_fifo_out = (GenericFifo<internal_flit_t>*) 127 127 malloc(sizeof(GenericFifo<internal_flit_t>) * (m_local_outputs + 1)); … … 179 179 //////////////////////////////////////////////////////////////////////////// 180 180 tmpl(size_t)::route( sc_uint<flit_width> data, // first flit 181 size_t input ) // input port index 181 size_t input ) // input port index 182 182 { 183 183 size_t output; // selected output port … … 185 185 size_t y_dest = (size_t)(data >> m_y_shift) & m_y_mask; 186 186 187 if ( (x_dest == m_local_x) and (y_dest == m_local_y) and 188 (m_local_outputs > 0) ) // local dest 187 // there are two types of local request: 188 // - when destination coordinates correspond to local coordinates 189 // - when there is a segment reallocation and the new host is local 190 // to support the second case, the locality of the global-to-local 191 // requests is not checked. 192 bool local_dest = ((x_dest == m_local_x) and (y_dest == m_local_y)) or 193 (input == m_local_inputs); 194 195 if ( local_dest and (m_local_outputs > 0) ) // local dest 189 196 { 190 197 if ( m_use_routing_table ) … … 194 201 { 195 202 uint64_t address; 196 if (flit_width >= m_addr_width) 203 if (flit_width >= m_addr_width) 197 204 address = data>>(flit_width - m_addr_width); 198 else 205 else 199 206 address = data<<(m_addr_width - flit_width); 200 207 output = m_cmd_rt[ address ]; 201 208 } 202 209 else 203 { 210 { 204 211 uint32_t srcid = data >> m_l_shift; 205 212 output = m_rsp_rt[ srcid ]; … … 209 216 { 210 217 output = (size_t)(data >> m_l_shift) & m_l_mask; 211 218 212 219 if ( output >= m_local_outputs ) 213 220 { … … 218 225 } 219 226 } 220 else // global dest 221 { 222 if ( input == m_local_inputs ) 223 { 224 std::cout << "ERROR in DSPIN_LOCAL_CROSSBAR: " << name() 225 << " illegal global to global request" << std::endl; 226 exit(0); 227 } 228 227 else // global dest 228 { 229 229 output = m_local_outputs; 230 230 } … … 243 243 const char* infsm_str[] = { "IDLE", "REQ", "ALLOC", "REQ_BC", "ALLOC_BC" }; 244 244 245 std::cout << "DSPIN_LOCAL_CROSSBAR " << name() << std::hex; 245 std::cout << "DSPIN_LOCAL_CROSSBAR " << name() << std::hex; 246 246 247 247 for( size_t i = 0 ; i <= m_local_inputs ; i++) // loop on input ports 248 248 { 249 std::cout << " / infsm[" << std::dec << i 249 std::cout << " / infsm[" << std::dec << i 250 250 << "] = " << infsm_str[r_fsm_in[i].read()]; 251 251 } … … 257 257 size_t in = r_index_out[out]; 258 258 std::cout << " / in[" << in << "] -> out[" << out << "]"; 259 } 259 } 260 260 } 261 261 std::cout << std::endl; … … 273 273 // control signals for the input fifos 274 274 bool fifo_in_write[m_local_inputs+1]; 275 bool fifo_in_read[m_local_inputs+1]; 275 bool fifo_in_read[m_local_inputs+1]; 276 276 internal_flit_t fifo_in_wdata[m_local_inputs+1]; 277 277 … … 281 281 internal_flit_t fifo_out_wdata[m_local_outputs+1]; 282 282 283 // reset 284 if ( p_resetn.read() == false ) 285 { 286 for(size_t j = 0 ; j <= m_local_outputs ; j++) 283 // reset 284 if ( p_resetn.read() == false ) 285 { 286 for(size_t j = 0 ; j <= m_local_outputs ; j++) 287 287 { 288 288 r_alloc_out[j] = false; … … 290 290 r_fifo_out[j].init(); 291 291 } 292 for(size_t i = 0 ; i <= m_local_inputs ; i++) 292 for(size_t i = 0 ; i <= m_local_inputs ; i++) 293 293 { 294 294 r_index_in[i] = 0; … … 300 300 301 301 // fifo_in signals default values 302 for(size_t i = 0 ; i < m_local_inputs ; i++) 303 { 304 fifo_in_read[i] = false; 302 for(size_t i = 0 ; i < m_local_inputs ; i++) 303 { 304 fifo_in_read[i] = false; 305 305 fifo_in_write[i] = p_local_in[i].write.read(); 306 306 fifo_in_wdata[i].data = p_local_in[i].data.read(); … … 313 313 314 314 // fifo_out signals default values 315 for(size_t j = 0 ; j < m_local_outputs ; j++) 315 for(size_t j = 0 ; j < m_local_outputs ; j++) 316 316 { 317 317 fifo_out_read[j] = p_local_out[j].read.read(); 318 fifo_out_write[j] = false; 318 fifo_out_write[j] = false; 319 319 } 320 320 fifo_out_read[m_local_outputs] = p_global_out.read.read(); 321 fifo_out_write[m_local_outputs] = false; 321 fifo_out_write[m_local_outputs] = false; 322 322 323 323 // loop on the output ports: … … 326 326 for ( size_t j = 0 ; j <= m_local_outputs ; j++ ) 327 327 { 328 if( r_alloc_out[j].read() and (r_fifo_out[j].wok()) ) 328 if( r_alloc_out[j].read() and (r_fifo_out[j].wok()) ) 329 329 { 330 330 get_out[j] = r_index_out[j].read(); 331 331 } 332 332 else 333 { 334 get_out[j] = 0xFFFFFFFF; 335 } 336 } 337 338 // loop on the input ports (including global input port, 333 { 334 get_out[j] = 0xFFFFFFFF; 335 } 336 } 337 338 // loop on the input ports (including global input port, 339 339 // with the convention index[global] = m_local_inputs) 340 // The port state is defined by r_fsm_in[i], r_index_in[i] 340 // The port state is defined by r_fsm_in[i], r_index_in[i] 341 341 // The req_in[i] computation uses the route() function. 342 342 // Both put_in[i] and req_in[i] depend on the input port state. … … 351 351 if ( r_fifo_in[i].rok() ) // packet available in input fifo 352 352 { 353 if ( is_broadcast(r_fifo_in[i].read().data ) and 353 if ( is_broadcast(r_fifo_in[i].read().data ) and 354 354 m_broadcast_supported ) // broadcast required 355 355 { … … 398 398 req_in[i] = 0xFFFFFFFF; // no request 399 399 if ( r_fifo_in[i].read().eop and 400 r_fifo_in[i].rok() and 400 r_fifo_in[i].rok() and 401 401 (get_out[r_index_in[i].read()] == i) ) // last flit transfered 402 402 { … … 416 416 break; 417 417 } 418 case INFSM_ALLOC_BC: // output port allocated 418 case INFSM_ALLOC_BC: // output port allocated 419 419 { 420 420 data_in[i] = r_fifo_in[i].read(); … … 422 422 req_in[i] = 0xFFFFFFFF; // no request 423 423 424 if ( r_fifo_in[i].rok() and 424 if ( r_fifo_in[i].rok() and 425 425 get_out[r_index_in[i].read()] == i ) // last flit transfered 426 426 { 427 if ( not r_fifo_in[i].read().eop ) 427 if ( not r_fifo_in[i].read().eop ) 428 428 { 429 429 std::cout << "ERROR in DSPIN_LOCAL_CROSSBAR " << name() … … 438 438 } // end switch 439 439 } // end for input ports 440 441 // loop on the output ports (including global output port, 440 441 // loop on the output ports (including global output port, 442 442 // with the convention index[global] = m_local_outputs) 443 443 // The r_alloc_out[j] and r_index_out[j] computation 444 444 // implements the round-robin allocation policy. 445 445 // These two registers implement a 2*N states FSM. 446 for( size_t j = 0 ; j <= m_local_outputs ; j++ ) 446 for( size_t j = 0 ; j <= m_local_outputs ; j++ ) 447 447 { 448 448 if( not r_alloc_out[j].read() ) // not allocated: possible new allocation 449 449 { 450 for( size_t k = r_index_out[j].read() + 1 ; 451 k <= (r_index_out[j].read() + m_local_inputs + 1) ; 452 k++ ) 453 { 450 for( size_t k = r_index_out[j].read() + 1 ; 451 k <= (r_index_out[j].read() + m_local_inputs + 1) ; 452 k++ ) 453 { 454 454 size_t i = k % (m_local_inputs + 1); 455 455 456 if( req_in[i] == j ) 456 if( req_in[i] == j ) 457 457 { 458 458 r_alloc_out[j] = true; … … 461 461 } 462 462 } // end loop on input ports 463 } 463 } 464 464 else // allocated: possible desallocation 465 465 { 466 466 if ( data_in[r_index_out[j]].eop and 467 r_fifo_out[j].wok() and 468 put_in[r_index_out[j]] ) 467 r_fifo_out[j].wok() and 468 put_in[r_index_out[j]] ) 469 469 { 470 470 r_alloc_out[j] = false; … … 474 474 475 475 // loop on input ports : 476 // fifo_in_read[i] computation 476 // fifo_in_read[i] computation 477 477 // (computed here because it depends on get_out[]) 478 for( size_t i = 0 ; i <= m_local_inputs ; i++ ) 479 { 480 if ( (r_fsm_in[i].read() == INFSM_REQ) or 478 for( size_t i = 0 ; i <= m_local_inputs ; i++ ) 479 { 480 if ( (r_fsm_in[i].read() == INFSM_REQ) or 481 481 (r_fsm_in[i].read() == INFSM_ALLOC) or 482 482 ((r_fsm_in[i].read() == INFSM_ALLOC_BC) and (r_index_in[i].read() == 0))) … … 485 485 } 486 486 if ( (r_fsm_in[i].read() == INFSM_IDLE) and 487 is_broadcast( r_fifo_in[i].read().data ) and 488 m_broadcast_supported ) 487 is_broadcast( r_fifo_in[i].read().data ) and 488 m_broadcast_supported ) 489 489 { 490 490 fifo_in_read[i] = true; … … 495 495 // The fifo_out_write[j] and fifo_out_wdata[j] computation 496 496 // implements the output port mux 497 for( size_t j = 0 ; j <= m_local_outputs ; j++ ) 497 for( size_t j = 0 ; j <= m_local_outputs ; j++ ) 498 498 { 499 499 if( r_alloc_out[j] ) // output port allocated … … 505 505 506 506 // input FIFOs update 507 for(size_t i = 0 ; i <= m_local_inputs ; i++) 507 for(size_t i = 0 ; i <= m_local_inputs ; i++) 508 508 { 509 509 r_fifo_in[i].update(fifo_in_read[i], … … 514 514 // output FIFOs update 515 515 for(size_t j = 0 ; j <= m_local_outputs ; j++) 516 { 516 { 517 517 r_fifo_out[j].update(fifo_out_read[j], 518 518 fifo_out_write[j], … … 525 525 { 526 526 // input ports 527 for(size_t i = 0 ; i < m_local_inputs ; i++) 527 for(size_t i = 0 ; i < m_local_inputs ; i++) 528 528 { 529 529 p_local_in[i].read = r_fifo_in[i].wok(); … … 532 532 533 533 // output ports 534 for(size_t j = 0 ; j < m_local_outputs ; j++) 534 for(size_t j = 0 ; j < m_local_outputs ; j++) 535 535 { 536 536 p_local_out[j].write = r_fifo_out[j].rok();
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