Changeset 99 for trunk/platforms
- Timestamp:
- Sep 30, 2010, 7:09:43 PM (14 years ago)
- Location:
- trunk/platforms
- Files:
-
- 6 edited
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caba-vdspin-vci_synthetic_initiator/Makefile (modified) (1 diff)
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caba-vdspin-vci_synthetic_initiator/platform_desc (modified) (1 diff)
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caba-vdspin-vci_synthetic_initiator/top.cpp (modified) (8 diffs)
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dsx/v1_1cluster_phys_dma/cluster.pyc (modified) (previous)
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dsx/v1_1cluster_phys_dma/transcript (modified) (2 diffs)
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dsx/v1_1cluster_phys_dma/vsim.wlf (modified) (previous)
Legend:
- Unmodified
- Added
- Removed
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trunk/platforms/caba-vdspin-vci_synthetic_initiator/Makefile
r97 r99 1 ARCH=mips32el 1 2 SIMULATION_ARGS=100000 2 3 #SOCLIB_CC_ADD_ARGS=-t systemcass 3 4 SOCLIB?=$(shell soclib-cc --getpath) 4 5 export SOCLIB 6 NO_SOFT=1 5 7 include $(SOCLIB)/soclib/platform/topcells/all.mk -
trunk/platforms/caba-vdspin-vci_synthetic_initiator/platform_desc
r97 r99 4 4 todo = Platform('caba', 'top.cpp', 5 5 uses = [ 6 Uses('caba:vci_synthetic_initiator') 6 Uses('caba:vci_synthetic_initiator'), 7 7 Uses('caba:vci_local_ring_fast', 8 8 ring_cmd_data_size = 40, -
trunk/platforms/caba-vdspin-vci_synthetic_initiator/top.cpp
r97 r99 8 8 #include "mapping_table.h" 9 9 #include "alloc_elems.h" 10 #include "vci_simple_ram.h" 11 #include "vci_multi_tty.h" 12 #include "vci_local_ring_network.h" 13 #include "vci_simple_ring_network.h" 14 #include "virtual_dspin_network.h" 10 //#include "vci_simple_ram.h" 11 //#include "vci_multi_tty.h" 12 #include "vci_local_ring_fast.h" 13 #include "virtual_dspin_router.h" 15 14 #include "vci_synthetic_initiator.h" 16 15 … … 37 36 using soclib::common::Segment; 38 37 38 using soclib::common::uint32_log2; 39 39 40 // Define VCI parameters 40 41 typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param; … … 44 45 soclib::common::MappingTable maptab(32, IntTab(2,10), IntTab(2,3), 0x00C00000); 45 46 46 maptab.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(2,1), true));47 maptab.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(2,1), true));48 maptab.add(Segment("tty" , TTY_BASE , TTY_SIZE , IntTab(3,1), false));49 47 50 48 maptab.add(Segment("mc_r0" , MC0_R_BASE , MC0_R_SIZE , IntTab(0,0), false, true, IntTab(0,0))); … … 64 62 sc_signal<bool> signal_resetn("resetn"); 65 63 66 soclib::caba::VciSignals<vci_param> * signal_vci_ini_synth = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth", N_CLUSTERS); 67 soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c0 = soclib::common::alloc_elems<solib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals", 2, Y_MAX, X_MAX, 5 ); 68 soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c1 = soclib::common::alloc_elems<solib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals", 2, Y_MAX, X_MAX, 5 ); 64 soclib::caba::VciSignals<vci_param> * signal_vci_ini_synth_c0 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth", N_CLUSTERS); 65 soclib::caba::VciSignals<vci_param> * signal_vci_ini_synth_c1 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth", N_CLUSTERS); 66 /////////////////////////////////////////////////////////////// 67 // VDSPIN Signals : one level for in and out, one level for X length in the mesh, 68 // one level for Y length in the mesh, last level for each port of the router 69 /////////////////////////////////////////////////////////////// 70 soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c0 = soclib::common::alloc_elems<solib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals_channel_0", 2, Y_MAX, X_MAX, 5 ); 71 soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c1 = soclib::common::alloc_elems<solib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals_channel_1", 2, Y_MAX, X_MAX, 5 ); 72 soclib::caba::DspinSignals<WIDTH_RSP> **** dspin_signals_rsp_c0 = soclib::common::alloc_elems<solib::caba::DspinSignals<WIDTH_RSP> >("Dspin_rsp_signals_channel_0", 2, Y_MAX, X_MAX, 5 ); 73 soclib::caba::DspinSignals<WIDTH_RSP> **** dspin_signals_rsp_c1 = soclib::common::alloc_elems<solib::caba::DspinSignals<WIDTH_RSP> >("Dspin_rsp_signals_channel_2", 2, Y_MAX, X_MAX, 5 ); 69 74 70 75 //soclib::caba::VciSignals<vci_param> * signal_vci_tgt_proc = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_tgt_proc", N_CLUSTERS); 71 76 72 77 // N_CLUSTERS ring. 73 soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ;78 soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring_c0 = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ; 74 79 for(int i = 0 ; i < N_CLUSTERS ; i++){ // ringid, fifo, fifo, nb_init, nb_tgt 75 new(&local_ring[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ("cluster" + i,maptab, IntTab(i), 2, 18, 1, 1) 80 new(&local_ring_c0[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ("cluster_c0" + i,maptab, IntTab(i), 2, 18, 1, 1) 81 } 82 83 soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring_c1 = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ; 84 for(int i = 0 ; i < N_CLUSTERS ; i++){ // ringid, fifo, fifo, nb_init, nb_tgt 85 new(&local_ring_c1[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ("cluster_c1" + i,maptab, IntTab(i), 2, 18, 1, 1) 76 86 } 77 87 … … 95 105 96 106 // N_CLUSTERS VCI Synthetic Initiator (1 initiator per cluster/network) 97 soclib::caba::VciSyntheticInitiator<vci_param> * initiator = (soclib::caba::VciSyntheticInitiator<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticInitiator<vci_param> )* N_CLUSTERS);107 soclib::caba::VciSyntheticInitiator<vci_param> * initiator_c0 = (soclib::caba::VciSyntheticInitiator<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticInitiator<vci_param> )* N_CLUSTERS); 98 108 for(int i = 0 ; i < Y_MAX; i++) 99 109 for(int j = 0 ; j < Y_MAX ; j++) 100 new(&initiator[Y_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> ("Initiator" + (Y_MAX*i+j), Y_MAX*i+j, maptab, IntTab(i,j),); 110 new(&initiator_c0[Y_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> ("Initiator_c0" + (i*X_MAX+j), i*X_MAX+j, maptab, IntTab(i,j),16, 0.5, 2, X_MAX, Y_MAX); 111 112 soclib::caba::VciSyntheticInitiator<vci_param> * initiator_c1 = (soclib::caba::VciSyntheticInitiator<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticInitiator<vci_param> )* N_CLUSTERS); 113 for(int i = 0 ; i < Y_MAX; i++) 114 for(int j = 0 ; j < Y_MAX ; j++) 115 new(&initiator_c1[Y_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> ("Initiator_c1" + (i*X_MAX+j), i*X_MAX+j, maptab, IntTab(i,j),16, 0.5, 2, X_MAX, Y_MAX); 101 116 102 117 /////////////////////////////////////////////////////////////// … … 104 119 /////////////////////////////////////////////////////////////// 105 120 for(int i = 0 ; i < N_CLUSTERS ; i++){ 106 local_ring[i].p_clk(signal_clk); 107 local_ring[i].p_resetn(signal_resetn); 108 local_ring[i].p_to_initiator[0](signal_vci_ini_synth[i]); 109 initiator[i].p_clk(signal_clk); 110 initiator[i].p_resetn(signal_resetn); 111 initiator[i].p_vci(signal_vci_ini_synth[i]); 121 local_ring_c0[i].p_clk(signal_clk); 122 local_ring_c0[i].p_resetn(signal_resetn); 123 local_ring_c0[i].p_to_initiator[0](signal_vci_ini_synt_c0h[i]); 124 initiator_c0[i].p_clk(signal_clk); 125 initiator_c0[i].p_resetn(signal_resetn); 126 initiator_c0[i].p_vci(signal_vci_ini_synth_c0[i]); 127 local_ring_c1[i].p_clk(signal_clk); 128 local_ring_c1[i].p_resetn(signal_resetn); 129 local_ring_c1[i].p_to_initiator[0](signal_vci_ini_synth_c1[i]); 130 initiator_c1[i].p_clk(signal_clk); 131 initiator_c1[i].p_resetn(signal_resetn); 132 initiator_c1[i].p_vci(signal_vci_ini_synth_c1[i]); 112 133 } 113 134 114 135 /////////////////////////////////////////////////////////////// 115 // Connection of each VDspin Router to each local ring 136 // Connection of each VDspin Router to each local ring and 137 // neighbors VDspin Router 116 138 /////////////////////////////////////////////////////////////// 117 139 for(int i = 0; i < Y_MAX ; i++){ … … 119 141 routers_cmd[i][j].p_clk(signal_clk); 120 142 routers_cmd[i][j].p_resetn(signal_resetn); 143 routers_rsp[i][j].p_clk(signal_clk); 144 routers_rsp[i][j].p_resetn(signal_resetn); 145 local_ring_c0[i*X_MAX+j].p_gate_cmd_in( dspin_signals_cmd_c0[0][i][j][LOCAL]); 146 local_ring_c0[i*X_MAX+j].p_gate_cmd_out(dspin_signals_cmd_c0[1][i][j][LOCAL] ); 147 local_ring_c0[i*X_MAX+j].p_gate_rsp_in( dspin_signals_rsp_c0[0][i][j][LOCAL]); 148 local_ring_c0[i*X_MAX+j].p_gate_rsp_out(dspin_signals_rsp_c0[1][i][j][LOCAL] ); 149 local_ring_c1[i*X_MAX+j].p_gate_cmd_in( dspin_signals_cmd_c1[0][i][j][LOCAL]); 150 local_ring_c1[i*X_MAX+j].p_gate_cmd_out(dspin_signals_cmd_c1[1][i][j][LOCAL] ); 151 local_ring_c1[i*X_MAX+j].p_gate_rsp_in( dspin_signals_rsp_c1[0][i][j][LOCAL]); 152 local_ring_c1[i*X_MAX+j].p_gate_rsp_out(dspin_signals_rsp_c1[1][i][j][LOCAL] ); 121 153 for(k = 0; k < 5; k++){ 122 154 if(i == 0){ … … 126 158 routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); 127 159 routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); 128 routers_rsp[i][j].p_out[0][k](dspin_signals_ cmd_c0[0][i][j][k]);129 routers_rsp[i][j].p_out[1][k](dspin_signals_ cmd_c1[0][i][j][k]);130 routers_rsp[i][j].p_in[0][k](dspin_signals_ cmd_c0[1][i][j][k]);131 routers_rsp[i][j].p_in[1][k](dspin_signals_ cmd_c1[1][i][j][k]);160 routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); 161 routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); 162 routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); 163 routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); 132 164 } else { 133 165 if(k == WEST){ 166 routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i][j-1][EAST]); 167 routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i][j-1][EAST]); 168 routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i][j-1][EAST]); 169 routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i][j-1][EAST]); 170 routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i][j-1][EAST]); 171 routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i][j-1][EAST]); 172 routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i][j-1][EAST]); 173 routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i][j-1][EAST]); 174 } else { 175 routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]); 176 routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]); 177 routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); 178 routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); 179 routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); 180 routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); 181 routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); 182 routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); 183 } 134 184 } 135 185 } else { 136 186 if(k == SOUTH){ 187 routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i-1][j][NORTH]); 188 routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i-1][j][NORTH]); 189 routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i-1][j][NORTH]); 190 routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i-1][j][NORTH]); 191 routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i-1][j][NORTH]); 192 routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i-1][j][NORTH]); 193 routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i-1][j][NORTH]); 194 routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i-1][j][NORTH]); 195 } else if(k == WEST){ 196 if(j == 0){ 197 routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]); 198 routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]); 199 routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); 200 routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); 201 routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); 202 routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); 203 routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); 204 routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); 205 } else { 206 routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i][j-1][EAST]); 207 routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i][j-1][EAST]); 208 routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i][j-1][EAST]); 209 routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i][j-1][EAST]); 210 routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i][j-1][EAST]); 211 routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i][j-1][EAST]); 212 routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i][j-1][EAST]); 213 routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i][j-1][EAST]); 214 } 215 } else { 216 routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]); 217 routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]); 218 routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]); 219 routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]); 220 routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]); 221 routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]); 222 routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]); 223 routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]); 224 } 137 225 } 138 226 } -
trunk/platforms/dsx/v1_1cluster_phys_dma/transcript
r93 r99 1 # // ModelSim SE 6.5c Aug 27 2009 Linux 2.6.18-164.1 5.1.el5PAE1 # // ModelSim SE 6.5c Aug 27 2009 Linux 2.6.18-164.11.1.el5 2 2 # // 3 3 # // Copyright 1991-2009 Mentor Graphics Corporation … … 12 12 # Loading /users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so 13 13 # Loading /users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work.system_driver 14 # Adding cellsize=4 15 # Adding plensize=8 16 # Adding addrsize=32 17 # Adding clensize=1 18 # Adding rerrorsize=1 19 # Adding srcidsize=14 20 # Adding pktidsize=4 21 # Adding trdidsize=4 22 # Adding wrplensize=1 23 # Adding burst_size=64 24 # Loading std.standard 25 # Loading ieee.std_logic_1164(body) 26 # Loading ieee.numeric_std(body) 27 # Loading ieee.std_logic_arith(body) 28 # Loading ieee.std_logic_unsigned(body) 29 # Refreshing /users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work.vci_dma(rtl) 30 # Loading work.vci_dma(rtl) 31 # Refreshing /users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work.credit_accountant(rtl) 32 # Loading work.credit_accountant(rtl) 33 run -all 34 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 35 # Time: 0 ns Iteration: 0 Instance: /system_driver/top/dma0/hdl/irq_set_reset 36 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 37 # Time: 0 ns Iteration: 0 Instance: /system_driver/top/dma0/hdl/irq_set_reset 38 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 39 # Time: 0 ns Iteration: 0 Instance: /system_driver/top/dma0/hdl/irq_set_reset 40 # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 41 # Time: 0 ns Iteration: 0 Instance: /system_driver/top/dma0/hdl/irq_set_reset 42 # Plwet 43 # Loading at 0xbfc00000 size 65536: .reset 44 # Loading at 0x80000000 size 65536: .excep 45 # Loading at 0x400000 size 327680: .text 46 # Loading at 0x10000000 size 1048576: .rodata .rel.dyn .sdata 47 # Break key hit 48 # Simulation stop requested. 14 49 quit 15 # Break key hit16 # ** Error: (vish-4000) A design must be loaded before the vsim_break command can be used.
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