Timeline



Dec 8, 2012:

5:01 PM Changeset [282] by bouyer
Complete r281: Keep BEV bit set in STATUS register, and add an …
4:59 PM Changeset [281] by bouyer
Keep BEV bit set in STATUS register, and add an exception handler at …
4:58 PM Changeset [280] by bouyer
Remove unused base_addresses

Dec 5, 2012:

6:55 PM Changeset [279] by cfuguet
Introducing multi block read in the ioc_read function for the FPGA platform

Dec 4, 2012:

1:31 PM Changeset [278] by bouyer
The ring is cpu-ungry, so give one thread per ring when running under …

Nov 30, 2012:

1:20 PM Changeset [277] by cfuguet
Fixing bug in the alloc dir FSM. The READ FSM release the lock on the …

Nov 29, 2012:

4:51 PM Changeset [276] by bouyer
A boot loader to be stored in ROM of a TSAR platform. Based on Cesar …
1:21 PM Changeset [275] by bouyer
This VHDL implementation uses rings, use rings here too.
12:57 PM Changeset [274] by bouyer
Add a platform describing as closely as possible the hardware that is …

Nov 28, 2012:

11:51 AM Changeset [273] by cfuguet
Modificating the VCI Memory Cache to align the VHDL and the SOCLIB …

Nov 25, 2012:

1:20 AM Changeset [272] by bouyer
Fix writes: - properly compute r_buf_address, + has highter priority …

Nov 24, 2012:

10:28 PM Changeset [271] by bouyer
Remove useless file.
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