Changes between Version 14 and Version 15 of AtomicOperations

Timestamp:

Dec 7, 2015, 8:49:15 PM (9 years ago)

Author:

alain

Comment:

--

AtomicOperations

@@ -9 +9 @@
  
  * The '''CAS''' (Compare and Swap) operation is implemented as a specific VCI transaction. As there is no CAS instruction in the MIPS32 instruction set, this operation cannot be used by the software. It is only used by some hardware components such as the L1 cache controller (to allow the MMU to update the DIRTY bit in the page tables), or by some DMA peripheral such as the vci_mwmr_dma component (to atomically access the lock protecting a shared communication channel).
+
+For both types of operation, the addresses a supposed to be aligned on 32 bits word boundaries, and the data are supposed to be 32 bits words.
 
 == 2.  LL/SC operation ==
@@ -96 +98 @@
 == 3.  CAS operation ==
 
+=== 3.1 general principle ===
 
-=== 3.1 new semantic ===
+The semantic of a CAS(X,D_old,D_new) transaction (three arguments in the VCI command) is the following:
 
-The formal semantic of a LL/SC access is :
-(1) The Store Conditional succeeds if there was no other Store Conditional at the same address since the last Linked Load.
+ * If the value stored at address X is equal to the D_old value, the CAS returns a ''success'' code in the VCI response, and the value D_new is written at address X.
+ * If the value stored at address X is not equal to the D_old value, the CAS returns a ''failure'' code in the VCI response, and no write is done at address X.
 
-The implemented semantic is :
-(2) The Store Conditional succeeds if the content of the memory has not changed since the last Linked Load.
+=== 3.2 Implementation ===
 
-Clearly we have (1) => (2) . But we have only (2) => (1) when the software does not use the LL/SC mechanism to monitor WRITEs. Such use of the LL/SC mechanism has to be avoided.
+This operation is implemented in the L2 cache controller.
 
-=== 3.2 new protocol ===
-
-In the new protocol, there is no more LL on the network : 
-
- * Linked Loads become simple Reads, where the data sent to the processor is recorded in a register of the L1 cache. When the processor issues a Store Conditional, the L1 cache sends a "SC" packet, where the first flits contain the data previously read and the next flits contain the data to write in the memory. So this new SC packet is 2 (32 bits accesses) or 4 flits (64 bits accesses) long.
-
- * The memory cache controller then compares the data read by the L1 cache to the data in the memory cache. If these two values are equal, the Store Conditional is done, and the response to the SC is success (0 value), else the Store Conditional is not done, and the response is failure (1 value). 
-
-=== 3.3 memory cache controller ===
-
-The memory cache controller does not have a linked access buffer any more. It simply has to be capable of recording pending Store Conditional in the table of transactions to the external RAM controller, in case of miss in the memory cache.
-
-The actions done by the memory cache controller for the various commands are described below :
-
-
-'''SC(SRCID, X)'''
-{{{
-  Read the data in the memory cache.
-  If ( data read by the L1 cache == data from the memory cache ) {
-      - write data in the memory cache
-      - send updates or invalidates to the owners of this cache line
-      - after all responses to UPDATE or INVALIDATE have been received, return true 
-        to the L1 cache.   
-  } else {
-      return false to the L1 cache
-  }
-}}}
-
-'''WRITE(SRCID, X)'''
-{{{
-  - Scan the linked list of copies to send an UPDATE request 
-    to the L1 caches (other than SRCID)
-  - Write data in the memory cache
-  - after all responses to UPDATE have been received, acknowledge the 
-    write request.
-}}}
-
-'''READ(SRCID, X)'''
-{{{
-  If ( cachable request ) {
-    - register the SRCID in the list of copies associated to the X address.
-    - return the complete or partial cache line
-  } else {
-    - return a single word.
-  }
-}}}
-
-=== 3.4  L1 cache controller ===
-
-The L1 cache controller receiving a new LL(X) request from the processor must locally register this request on the X address and the data sent to the processor. When it receives a SC(X) request from the processor, it checks the LL register and, if this register is valid, it sends a Store Conditional to the memory cache controller containing both the data read by the LL(X) and the data to write. This requires an extra register to store the address, the data, a VALID flip-flop, and a LONG flip-flop (in case of 64 bits LL/SC) in the L1 cache controller.
-
-The actions done by the L1 cache controller for the various commands are described below :
-
-'''LL(X) from processor'''
-{{{
-  If (VALID = true & ADDRESS = X) {    // local spin-lock         
-    return the read data to the processor
-  } else {                                          // first LL access                       
-    VALID <= true
-    ADDRESS <= X
-    DATA <= READ(X),
-    and return the read value to the processor
-  } 
-}}} 
-
-'''SC(X) from processor'''
-{{{
-  If (VALID = true & ADDRESS = X)  {    // possible success
-    send a SC(X) request to the memory cache containing the data stored in the LL register and the data to write,
-    and return the Boolean response to the processor
-    VALID <= false
-  } else {                                         // failure  
-   return a false value to the processor
-   VALID <= false
-  }
-}}}
-
-'''INVAL(L) or UPDATE(L) from memory controller'''
-{{{
-  The LL register must not be invalidated.
-  The L1 cache is updated or invalidated.
-}}}