Changes between Version 25 and Version 26 of AtomicOperations

Timestamp:

Oct 8, 2019, 4:36:49 PM (5 years ago)

Author:

alain

Comment:

--

AtomicOperations

@@ -49 +49 @@
 
 We summarize below the actions done by the L1 cache controller receiving a LL(X), SC(X,D) or SW(X,D) request from the processor: 
- * '''LL(X)''' : The L1 cache registers the X address and its local reservation register, activates the cycle counter, and send a single flit VCI LL command containing the X address to the L2 cache. When the response is received from the L2 cache containg the value and the key K, the key is saved in the local reservation register and the value is send to the processor.
+ * '''LL(X)''' : The L1 cache registers the X address and its local reservation register, activates the cycle counter, and send a single flit VCI LL command containing the X address to the L2 cache. The response received from the L2 cache contains both the read value D and the key K. The key is saved in the local reservation register and the value is send to the processor.
  * '''SC(X,D)''' : The L1 cache checks the X address agains the registered address. In case of miss, it returns a ''failure'' code to the processor, without any VCI transaction on the network. In case of hit, it invalidates the local reservation and sent a two flits VCI SC command containing the X address, the registered K value, and the D value.
  * '''SW(X,D)''' : The L1 cache checks the X address against the registered address. In case of hit the reservation is invalidated. In case of miss, the reservation is not modified. In both cases the write request is sent to the L2 cache.