Changes between Version 6 and Version 7 of AtomicOperations

Timestamp:

Jul 10, 2009, 10:34:21 AM (15 years ago)

Author:

choichil

Comment:

Some orthographic corrections

AtomicOperations

@@ -43 +43 @@
 === 3.1 memory cache controller ===
 
-The memory cache controller contains a dedicated storage that is used to register, for each cache line the set of  L1 caches that have copies. These sets of copies are implemented as linked lists of SRCIDs. To implement the Reservation Table, we just introduce, for each registered copy of a cache line, (i.e. each entry in this Reservation Table) one extra bit  to register a pending LL/SC atomic operation. 
+The memory cache controller contains a dedicated storage that is used to register, for each cache line the set of  L1 caches that have copies. These sets of copies are implemented as linked lists of SRCIDs. To implement the Reservation Table, we just introduce, for each registered copy of a cache line, (i.e. each entry in this Reservation Table) one extra bit to register a pending LL/SC atomic operation. 
 This approach is scalable, but creates the possibility of “false conflicts”, when several atomic access are done to the same cache line.
 
@@ -59 +59 @@
  }}}
 
-'''SC(SRCID, X)
+'''SC(SRCID, X)'''
 {{{
   Scan all copies associated to the cache line containing the X address
@@ -94 +94 @@
 === 3.2  L1 cache controller ===
 
-The L1 cache controller receiving a  new LL(X) request from the processor must locally register this reservation on the X address to validate the use of the locally cached copy, and to check the address when it receives a SC(X) request from the processor. This requires an extra register to store the address, and a RESERVED flip-flop in the L1 cache controller.
+The L1 cache controller receiving a new LL(X) request from the processor must locally register this reservation on the X address to validate the use of the locally cached copy, and to check the address when it receives a SC(X) request from the processor. This requires an extra register to store the address, and a RESERVED flip-flop in the L1 cache controller.
 
 The actions done by the L1 cache controller for the various commands are described below :
@@ -112 +112 @@
 '''SC(X) from processor'''
 {{{
-  If (RESERVED = true & ADDRESS = X)  {    // possible succès
+  If (RESERVED = true & ADDRESS = X)  {    // possible success
     send a SC(X) request to the memory cache,
     and return the Boolean response to the processor