Changes between Version 9 and Version 10 of CacheCoherence

Timestamp:

Feb 7, 2010, 4:06:10 PM (15 years ago)

Author:

alain

Comment:

--

CacheCoherence

@@ -16 +16 @@
 
 The basic mechanism is the following : when the memory controller receives a WRITE request for a given cache line, 
-he must send an UPDATE or INVALIDATE request to all L1 caches containing a copy (but the writer). 
-The write request is acknowledged only when all UPDATE or INVALIDATE transactions are completed. 
+he must send an UPDATE or INVAL request to all L1 caches containing a copy (but the writer). 
+The write request is acknowledged only when all UPDATE or INVAL transactions are completed. 
 
 In the TSAR architecture, the memory controller is distributed, as it is implemented by the distributed memory caches 
@@ -26 +26 @@
 In case of MISS, the memory cache controller must evict a victim line to bring in the missing line. In order to maintain the inclusive property, 
 all copies of the evicted cache line in L1 caches must be invalidated. To do it, the memory cache controller must send 
-INVALIDATE requests to all L1 caches containing a copy.
+invalidate requests to all L1 caches containing a copy.
 
 The TSAR architecture wants to guaranty the cache coherence by hardware, for both the data and instruction L1 caches. 
 The modifications of shared data are very frequent events, but the number of copies is generally not very high. 
-The modifications of shared code are very rare events ( self modifying code, or dynamic libraries ), but the number 
+The modifications of shared code are very rare events (self modifying code, or dynamic libraries), but the number 
 of replicated copies can be very large ( the exception handler, or the libc are generally replicated in all L1 caches ).
 Reflecting the different behaviour of data & instruction caches, the "hybrid" cache coherence protocol DHCCP defines two different strategies, 
@@ -36 +36 @@
  * '''MULTICAST_UPDATE''' :  When the number of copies is smaller than the DHCCP threshold, the memory cache controller registers the locations 
 of all the copies, and send a ''multicast_update'' transaction to each concerned L1 cache in case of modification.
- * '''BROADCAST_INVALIDATE''' :  When the number of copies is larger than the DHCCP threshold, the memory cache controller registers only the number 
+ * '''BROADCAST_INVAL''' :  When the number of copies is larger than the DHCCP threshold, the memory cache controller registers only the number 
 of copies (without localization) and send a ''broadcast_invalidate'' transaction  to all L1 caches in case of modication.  
 
@@ -43 +43 @@
 Three types of transactions, have been identified :
  * Direct transactions : READ / WRITE / LL / SC 
- * Coherence transactions : MULTI_UPDATE / MULTI_INVALIDATE / BROADCAST_INVALIDATE / CLEANUP
+ * Coherence transactions : MULTI_UPDATE / MULTI_INVAL / BROADCAST_INVAL / CLEANUP
  * External transactions : PUT / GET
         
@@ -52 +52 @@
 Symmetrically, a WRITE command packet contains N flits, and the corresponding WRITE response packet contains one single flit.
 
-There is one exception : For a BROADCAST_INVALIDATE transaction, the initiator sends one single flit VCI packet, 
+There is one exception : For a BROADCAST_INVAL transaction, the initiator sends one single flit VCI packet, 
 but receives several single flit VCI response packets.
   
@@ -84 +84 @@
 updated or invalidated before the WRITE transaction is acknowledged. 
 
- * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperations). For both a  LL (Linked Load) or a SC (Store Conditionnal) transaction, the VCI command packet and the VCI response packet contain one single VCI flit. The VCI CMD field must contain the VCI_LINKED_READ value (resp. VCI_STORE_CONDITIONNAL value). The VCI VCI PKTID and TRDID fields are not used.
+ * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperations). 
+For both a  LL (Linked Load) or a SC (Store Conditionnal) transaction, the VCI command packet and the VCI response packet 
+contain one single VCI flit. The VCI CMD field must contain the VCI_LINKED_READ value (resp. VCI_STORE_CONDITIONNAL value). 
+The VCI VCI PKTID and TRDID fields are not used.
 
 === 2.2 Coherence transactions ===
 
-For each cache line stored in the memory cache, the memory cache implement a Registration Table that contain the copies replicated 
+For each cache line stored in the memory cache, the memory cache implements a Registration Table that contain the copies replicated 
 in the L1 caches. Each entry in this Registration Table contains the SRCID of the L1 cache that contains a copy, as well as the type 
 of the copy (instruction/data). When the same cache line is replicated in both the instruction cache and the data cache of a processor, 
@@ -97 +100 @@
 All these transactions are write transactions.
   
- * A '''MULTICAST_UPDATE''' transaction is a multi-cast transaction sent by the memory cache controller when it receives a WRITE request 
+ * A '''MULTI_UPDATE''' transaction is a multi-cast transaction sent by the memory cache controller when it receives a WRITE request 
 to a replicated cache line and the number of copies does not exceeds the DHCCP threshold. It sends as many VCI transactions as the number 
 of registered copies (but the writer). The VCI command packet contains (N+2) flits. The VCI ADDRESS field is constant and contains the address 
@@ -108 +111 @@
 of the MULTICAST_UPDATE transaction.
 
- * A '''MULTICAST_INVALIDATE''' transaction is a multi-cast transaction, that is composed of several VCI transactions. When a memory cache makes a cache line 
+ * A '''MULTI_INVAL''' transaction is a multi-cast transaction, that is composed of several VCI transactions. When a memory cache makes a cache line 
 replacement (following a MISS in the memory cache), and the victim line has a number of copies smaller than the DHCCP threshold, it sends as many VCI transactions 
 as the number of registered copies. Both the VCI command packet and the VCI response packet contain only one flit. The VCI ADDRESS field contains the address