Changes between Version 13 and Version 14 of CacheCoherence


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Timestamp:
Jun 8, 2010, 9:43:02 AM (15 years ago)
Author:
alain
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  • CacheCoherence

    v13 v14  
    5959the target is a memory cache controller, acting as a physical memory bank, or another VCI target peripheral. This target can be located in any cluster.
    6060
    61 The L1 cache controller can issue several simultaneous VCI transactions, that must be distinguished by the PKTID field value. The VCI TRDID field is not used.
     61The L1 cache controller can issue several simultaneous VCI transactions, that must be distinguished by the VCI TRDID field value. The VCI PKTID field is not used.
    6262
     63 * A '''READ''' transaction can be a single word request (in case of uncached access), or a burst, corresponding to a complete cache line (16 words). A READ burst transaction initiated by any DMA controller must respect the same 16 words cache line format. For all READ transaction, the VCI command packet contains one single VCI flit. The  VCI CMD field contains the VCI_READ code. The VCI PLEN field is used to define the burst length (number of bytes). A READ transaction has a type, encoded in the three LSB bits of the VCI PKTID field, and the the MSB bit must be 0.
    6364
    64  * A '''READ''' transaction can be a single word request (in case of uncached access), or a burst, corresponding to a complete cache line (16 words). A READ burst transaction initiated by any DMA controller must respect the same 16 words cache line format. For all READ transaction, the VCI command packet contains one single VCI flit. The  VCI CMD field contains the VCI_READ code. The VCI PLEN field is used to define the burst length (number of bytes). A READ transaction has a type, encoded in the three LSB bits of the VCI PKTID field, and the the LSB bit must be 0.
     65|| TRDID for Uncached Data        ||0...00||
     66|| TRDID for Uncached Instruction ||0...01||
     67|| TRDID for Cached Data          ||0...10||
     68|| TRDID for Cached Instruction   ||0...11||
    6569
    66 || Uncached Data        ||000||
    67 || Uncached Instruction ||010||
    68 || Cached Data          ||100||
    69 || Cached Instruction   ||110||
     70 * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint. The VCI CMD field contains the VCI_WRITE code. The MSB bit of the TRDID field must be 1. The other bits in the TRDID field are used to code the slot index in the write buffer. If the modified cache line is replicated in one or several other L1 caches, the memory cache must guaranty that all copies have been updated or invalidated before the WRITE transaction is acknowledged.
    7071
    71  * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint. The VCI CMD field contains the VCI_WRITE code. The LSB bit of the PKTID field has the value 1. The other bits in the PKTID field can be used to code the slot index in the write buffer. If the modified cache line is replicated in one or several other L1 caches, the memory cache must guaranty that all copies have been updated or invalidated before the WRITE transaction is acknowledged.
     72|| TRDID for Write burst       ||1 wbuf_index||
    7273
    7374 * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperations).
    74 For both a  LL (Linked Load) or a SC (Store Conditionnal) transaction, the VCI command packet and the VCI response packet contain one single VCI flit. The VCI CMD field must contain the VCI_LINKED_READ value (resp. VCI_STORE_CONDITIONNAL value). The VCI PKTID field takes the 0 value for all LL or SC packets.
     75For both a  LL (Linked Load) or a SC (Store Conditionnal) transaction, the VCI command packet and the VCI response packet contain one single VCI flit. The VCI CMD field must contain the VCI_LINKED_READ value (resp. VCI_STORE_CONDITIONNAL value). The VCI TRDID field takes the 0 value for all LL or SC packets.
    7576
    7677=== 2.2 Coherence transactions ===
    … …  
    8788 * A '''BROADCAST_INVAL''' transaction is a broadcast transaction. This transaction is initiated when a memory cache controller replaces a line, or receives a WRITE request to a replicated cache line, and this cache line has a number of copies larger than the DHCCP threshold. The VCI command packet contains one single flit. This packet is replicated and dynamically broadcasted by the network itself. The VCI CMD field contains the VCI_WRITE code. The VCI ADDRESS field contains the global broadcast address 0x0000000003 (only the two LSB bits are set). The VCI WDATA and the VCI BE (the two LSB bits) field contain the line index. This VCI command is broadcasted to all L1 caches in the system, but only L1 caches that have a copy send a VCI response packet. All VCI response packets are independently returned to the memory cache initiator, that counts the number of VCI responses to detect the completion of the BROADCAST_INVAL transaction. If a L1 cache contains two copies of a cache line (i.e. the line is replicated in both the DATA cache, and the INSTRUCTION cache), it must send two VCI responses.
    8889
    89  * A '''CLEANUP''' transaction is initiated by a L1 cache controller to a memory cache controller, to signal that a cache line copy has been removed from an instruction or data cache. Both the VCI command packet and the VCI response packet contain one single flit. For a CLEANUP transaction, the VCI ADDRESS field must contain the removed cache line address.
     90 * A '''CLEANUP''' transaction is initiated by a L1 cache controller to a memory cache controller, to signal that a cache line copy has been removed from an instruction or data cache. Both the VCI command packet and the VCI response packet contain one single flit. For a CLEANUP transaction, the VCI ADDRESS field must contain the removed cache line address. The VCI TRDID fiels contains the value 0 for a data cache cleanup, and contains the value 1 for an instruction cache cleanup.
    9091
    9192=== 2.3 External transactions ===
    … …  
    101102As the memory cache controller can process several external transactions simultaneously, the VCI TRDID field contains the transaction index.
    102103
    103  * For a '''GET''' transaction, the VCI command packet contains one single flit. The VCI CMD field contains the READ value.
    104 The VCI response packet contains 8 flits (corresponding to the 64 bytes of a cache line).
     104 * For a '''GET''' transaction, the VCI command packet contains one single flit. The VCI CMD field contains the READ value. The VCI response packet contains 8 flits (corresponding to the 64 bytes of a cache line).
    105105
    106  * For a '''PUT''' transaction, the VCI command packet contains 8 flits. The VCI CMD field contains the WRITE value.
    107 The VCI response packet contains 1 flit.
     106 * For a '''PUT''' transaction, the VCI command packet contains 8 flits. The VCI CMD field contains the WRITE value. The VCI response packet contains 1 flit.
    108107
    109108