Changes between Version 16 and Version 17 of CacheCoherence


Ignore:
Timestamp:
Oct 2, 2011, 12:59:14 PM (13 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • CacheCoherence

    v16 v17  
    8888 * A '''BROADCAST_INVAL''' transaction is a broadcast transaction. This transaction is initiated when a memory cache controller replaces a line, or receives a WRITE request to a replicated cache line, and this cache line has a number of copies larger than the DHCCP threshold. The VCI command packet contains one single flit. This packet is replicated and dynamically broadcasted by the network itself. The VCI CMD field contains the VCI_WRITE code. The VCI ADDRESS field contains the global broadcast address 0x0000000003 (only the two LSB bits are set). The VCI WDATA and the VCI BE (the two LSB bits) field contain the line index. This VCI command is broadcasted to all L1 caches in the system, but only L1 caches that have a copy send a VCI response packet. All VCI response packets are independently returned to the memory cache initiator, that counts the number of VCI responses to detect the completion of the BROADCAST_INVAL transaction. If a L1 cache contains two copies of a cache line (i.e. the line is replicated in both the DATA cache, and the INSTRUCTION cache), it must send two VCI responses.
    8989
     90The following table defines the coherence command encoding (4 LSB bits in the VCI ADDRESS field)
     91|| COMMAND TYPE           ||    ||
     92|| Invalidate Data        ||0000||
     93|| Invalidate Instruction ||0100||
     94|| Update Data            ||1000||
     95|| Update Instruction     ||1100||
     96
    9097 * A '''CLEANUP''' transaction is initiated by a L1 cache controller to a memory cache controller, to signal that a cache line copy has been removed from an instruction or data cache. Both the VCI command packet and the VCI response packet contain one single flit. For a CLEANUP transaction, the VCI ADDRESS field must contain the removed cache line address. The VCI TRDID fiels contains the value 0 for a data cache cleanup, and contains the value 1 for an instruction cache cleanup.
    9198