Changes between Version 2 and Version 3 of CacheCoherence


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Timestamp:
Jul 1, 2009, 6:46:21 PM (15 years ago)
Author:
alain
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  • CacheCoherence

    v2 v3  
    2424Three types of transactions, have been identified :
    2525 * Direct transactions : READ / WRITE / LL / SC
    26  * Coherence transactions : UPDATE / INVALIDATE / CLEANUP
     26 * Coherence transactions : MULTI_UPDATE / MULTI_INVAL / BROADCAST_INVAL / CLEANUP
    2727 * External Transactions : PUT / GET
    2828       
    … …  
    3333There is one exception : For a BROADCAST_INVALIDATE transaction, the initiator sends one single flit VCI packet, but receives several single flit VCI response packets (see section 2.2).
    3434 
    35 === 2.1  READ / WRITE / LL / SC ===
     35=== 2.1  READ / WRITE / LL / SC transactions ===
    3636 
    3737These transactions are initiated by a processor (actually the L1 cache controller), or by another initiator ( an I/O peripheral or hardware coprocessor with a DMA capability). This initiator can be located in any cluster. For those transactions, the target is a memory cache controller, acting as a physical memory bank, or another VCI target peripheral. This target can be located in any cluster.
    … …  
    4141 * A '''WRITE''' transaction can be a single word request or a variable length burst request. In case of burst, the the VCI command packet contains at most 8 VCI flits, with consecutive addresses. All words belong to the same half cache line, and the VCI BE field can have different values for each flit (including the zero value). The VCI response packet contains one VCI flit. A WRITE burst transaction initiated by any DMA controller must respect the same 8 aligned words constraint.  The VCI CMD field contains the VCI_WRITE code. When the VCI TRDID field contains a non-zero value, it signals that the write request is “posted” : The VCI target must send a response to respect the VCI protocol, but this response can be send before the write is actually performed. This can be used by by the VCI/HT bridge. The VCI PKTID fields is not used. If the modified cache line is replicated in one or several other L1 caches, all copies must be updated or invalidated before the WRITE transaction is acknowledged.
    4242
    43  * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperation). For both a  LL (Linked Load) or a SC (Store Conditionnal) transaction, the VCI command packet and the VCI response packet contain one single VCI flit. The VCI CMD field must contain the VCI_LINKED_READ value (resp. VCI_STORE_CONDITIONNAL) value. The VCI VCI PKTID and TRDID fields are not used.
     43 * The TSAR architecture supports the '''LL/SC''' mechanism for atomic operations (see AtomicOperations). For both a  LL (Linked Load) or a SC (Store Conditionnal) transaction, the VCI command packet and the VCI response packet contain one single VCI flit. The VCI CMD field must contain the VCI_LINKED_READ value (resp. VCI_STORE_CONDITIONNAL) value. The VCI VCI PKTID and TRDID fields are not used.
    4444
    45 === 2.2 MULTI_UPDATE / MULTI_INVAL / BROADCAST_INVAL / CLEANUP
    46 These transactions are initiated by a memory cache controller to update or invalidate copies in the L1 caches. For each cache line stored in the memory cache, the memory cache handles an INS bit indicating that this cache line is replicated in at least one L1 instruction cache. This bit is set as soon as the memory cache receives a cache line READ request with the INS bit set in the TRDID field. When the cache line is marked as data  (INS = 0), the memory cache handles an explicit set of the SRCIDs of all L1 caches  containing a copy. When the cache line is marked as instruction (INS = 1), the memory cache handles a counter containing the number of copies in L1 caches.
     45=== 2.2 MULTI_UPDATE / MULTI_INVAL / BROADCAST_INVAL / CLEANUP transactions ===
     46
     47These 4 transactions implement the DHCCP protocol : For each cache line stored in the memory cache, the memory cache implement a Registration Table that contain the copies replicated in the L1 caches. Each entry in this Registration Table contains the SRCID of a L1 cache that contains a copy, as well as the type of the copy (instruction/data). When the same cache line is replicated in both the instruction cache and the data cache of a processor, this defines two separated entries in the Registration Table. When the number copies for a given cache line L exceeds the DHCCP threshold, the corresponding Registration Table is flushed, and the memory cache register only the number of copies.
    4748 
    48 •       A MULTI_UPDATE transaction is a multi-cast transaction, that is composed of several VCI transactions. When a memory cache controller receives a WRITE request to a replicated cache line marked as data (INS = 0) , it sends as many VCI transactions as the number of registered copies (but the writer). The VCI command packet contains (N+2) flits. The VCI ADDRESS field is constant & contains the address of the memory mapped UPDATE register in the L1 cache. The VCI CMD field contains the WRITE value. As the memory cache controller can handle several update/invalidate transactions simultaneously, the VCI TRDID field contains the transaction index. The VCI PLEN field contains the value  4*N, where N is the actual number of modified words in the cache line. The VCI WDATA field contains the line index in the first flit (30 bits), the first modified word index (4 bits) in the second flit, and the N modified words in the N following flits. For each modified word, the VCI BE field can have a different value (including the 0x0 value). The VCI response packet contains one single flit. The memory cache controller counts the number of VCI responses to detect the completion of the MULTI_UPDATE transaction.
     49 * A '''MULTI_UPDATE''' transaction is a multi-cast transaction sent by the memory cache controller when it receives a WRITE request to a replicated cache line and the number of copies does not exceeds the DHCCP threshold. It sends as many VCI transactions as the number of registered copies (but the writer). The VCI command packet contains (N+2) flits. The VCI ADDRESS field is constant & contains the address of the memory mapped UPDATE register in the L1 cache. The VCI CMD field contains the WRITE value. As the memory cache controller can handle several simultaneous update/invalidate transactions, the VCI TRDID field contains the transaction index. The VCI PLEN field contains the value  4*N, where N is the actual number of modified words in the cache line. The line index (34 bits) is transported in the VCI WDATA and VCI BE fields, of the first flit. The first modified word index (3 bits) is transported in the WDATA field of the second flit, and the N modified words in the WDATA and BE fields of the N following flits. For each modified word, the VCI BE field can have a different value (including the 0x0 value). The VCI response packet contains one single flit. The memory cache controller counts the number of VCI responses to detect the completion of the MULTI_UPDATE transaction.
    4950
    50 •       A MULTI_INVAL transaction is a multi-cast transaction, that is composed of several VCI transactions. When a memory cache makes a cache line replacement (following a MISS), and the victim line has the data type (INS = 0), it sends as many VCI transactions as the number of registered copies. Both the VCI command packet and the VCI response packet contain only one flit. The VCI CMD field contains the WRITE value. The VCI ADDRESS field contains the address of the memory mapped INVAL register in the L1 cache. The VCI CMD field contains the WRITE value. As the memory cache controller can handle several update/invalidate transactions simultaneously, the VCI TRDID field contains the transaction index.The VCI WDATA field contains the line index. The memory cache controller counts the number of VCI responses to detect the completion of the  MULTI_INVAL transaction.
     51 * A '''MULTI_INVAL''' transaction is a multi-cast transaction, that is composed of several VCI transactions. When a memory cache makes a cache line replacement (following a MISS), and the victim line has the data type (INS = 0), it sends as many VCI transactions as the number of registered copies. Both the VCI command packet and the VCI response packet contain only one flit. The VCI CMD field contains the WRITE value. The VCI ADDRESS field contains the address of the memory mapped INVAL register in the L1 cache. The VCI CMD field contains the WRITE value. As the memory cache controller can handle several update/invalidate transactions simultaneously, the VCI TRDID field contains the transaction index.The VCI WDATA field contains the line index. The memory cache controller counts the number of VCI responses to detect the completion of the  MULTI_INVAL transaction.
    5152
    5253•       A BROADCAST_INVAL transaction is a broadcast transaction. This transaction is initiated when a memory cache controller replace a line that has the instruction type (INS = 1), or when the memory cache receives a WRITE request to a replicated cache line that has the instruction type (INS = 1). The VCI command packet contains one single flit. This packet is replicated & dynamically broadcasted by the network itself. The VCI CMD field contains the WRITE value. The VCI ADDRESS field contains the global broadcast address 0x000000003 (only the two LSB bits are set). The VCI WDATA field contains the line index. This VCI command is broadcasted to all L1 caches in the system, but only L1 caches that have a copy send a VCI response packet. All VCI response packets are independently returned to the memory cache initiator, that counts the number of VCI responses to detect the completion of the BROADCAST_INVAL transaction. If a L1 cache contains two copies of a cache line (i.e. the line is replicated in both the DATA cache, and the INSTRUCTION cache), it must send two VCI responses.