Changes between Version 3 and Version 4 of CacheCoherence

Timestamp:

Jul 2, 2009, 10:10:05 AM (15 years ago)

Author:

alain

Comment:

--

CacheCoherence

@@ -16 +16 @@
 In case of MISS, the memory cache controller must evict a victim line to bring in the missing line. In order to maintain the inclusive property, all copies of the evicted cache line in L1 caches must be invalidated. To do it, the memory cache controller must send INVALIDATE requests to all L1 caches containing a copy.
 
-The TSAR architecture wants to guaranty the cache coherence by hardware, for both the data and instruction caches (L1 caches). Reflecting the different behaviour of data & instruction caches, the DHCCP protocol defines different strategies, depending on the number of copies :
- * Regarding the data, the modifications of shared data are very frequent events, but – in average – the number of copies is not very high. Therefore, the DHCCP protocol will preferably use a ''multicast/update'' strategy for the data caches.
+The TSAR architecture wants to guaranty the cache coherence by hardware, for both the data and instruction L1 caches. Reflecting the different behaviour of data & instruction caches, the DHCCP protocol defines two different strategies, depending on the number of copies :
+ * '''MULTICAST_UPDATE''' :  the modifications of shared data are very frequent events, but – in average – the number of copies is not very high. Therefore, when the number of copies is smaller than a given threshold, the cache controller registers the locations of all the copies, and use a ''multicast/update'' transaction.
  * Regarding the instructions, the modifications of shared code are rather rare events ( in case of self modifying code, or dynamic libraries ), but the number of replicated copies can be very large ( the system call handler, or the libc are likely replicated in all L1 caches ). Therefore, the DHCCP ptotocol will generally use a ''broadcast/invalidate'' policy for instruction caches.