Changes between Version 15 and Version 16 of InterconnexionNetworks


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Timestamp:
Jul 2, 2009, 6:52:52 PM (15 years ago)
Author:
alain
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  • InterconnexionNetworks

    v15 v16  
    5555Therefore, the total SRCID width cannot be larger than 14 bits.
    5656
    57 === 2.3  VCI Address generation on the coherence network ===
    58  
    59 This general indexing policy simplifies the VCI address generation on the coherence network :
    60 
    61  * In a '''multicast''' command packet from a memory cache controller to a L1 cache controller, the address is obtained by copying the target L1 cache SRCID in the MSB bits of the VCI ADDRESS (left aligned) : The L1 cache L_ID is actually used as the LADR address field. UPDATE/INVAL requests are distinguished by the bit ADDRESS[2] (0 for INVAL, 1 for UPDATE).
    62 
    63  * In a '''cleanup''' command packet from a L1 cache controller to a memory cache controller, the address is obtained by copying the (NX + NY) MSB bits of the line address in the VCI ADDRESS field (left aligned). The 0 value for the LADR address field is used to select the memory cache.
    64 
    65  * In a '''broadcast_invalidate''' command packet, the  ADDRESS[1:0] bits must be equal to 0x3. The 20 bits ADDRESS[21:2] will be used in a future extension of the DSPIN network to define the bounding box of a limited broadcast
    66 
    6757== 3.  Direct Network & Coherence Network ==
    6858
    … …  
    7464 * The '''global interconnect''' is implemented as one DSPIN network, supporting two virtual sub-networks, and the coherence sub-network supports a broadcast service for single flit VCI commands.
    7565
    76 === 3.1  DSPIN Packet format ===
     66=== 3.1  VCI Address generation ===
     67
     68On the direct network, the addresses are controlled by the software.
     69
     70On the coherence network, the addresses are defined by the hardware with the following policy:
     71
     72 * In a '''multicast''' command packet from a memory cache controller to a L1 cache controller, the address is obtained by copying the target L1 cache SRCID in the MSB bits of the VCI ADDRESS (left aligned) : The L1 cache L_ID is actually used as the LADR address field. UPDATE/INVAL requests are distinguished by the bit ADDRESS[2] (0 for INVAL, 1 for UPDATE).
     73
     74 * In a '''cleanup''' command packet from a L1 cache controller to a memory cache controller, the address is obtained by copying the (NX + NY) MSB bits of the line address in the VCI ADDRESS field (left aligned). The 0 value for the LADR address field is used to select the memory cache.
     75
     76 * In a '''broadcast_invalidate''' command packet, the  ADDRESS[1:0] bits must be equal to 0x3. The 20 bits ADDRESS[21:2] will be used in a future extension of the DSPIN network to define the bounding box of a limited broadcast
     77
     78=== 3.2 VCI parameters ===
     79
     80All Hardware components connected to the direct network or to the coherence network  respect the VCI/OCP communication interface.
     81
     82The direct network, and the coherence network being ''time-multiplexed'' on the DSPIN infrastructure, have identical VCI parameters :
     83
     84|| VCI Field              ||  width  ||
     85||                              ||              ||
     86||ADDRESS                || 40 bits ||
     87||WDATA , RDATA || 32 bits ||
     88||PLEN                   || 8   bits ||
     89||SRCID, RSRCID  || 14 bits ||
     90||TRDID, RTRDID  || 4   bits  ||
     91||PKTID, RPKTID || 4   bits   ||       
     92||RERROR                || 2   bits   ||       
     93
     94The TSAR architecture uses three values for the VCI RERROR field, in order to simplify the VCI/DSPIN wrapper, and to reduce the DSPIN Write Response packet length to one flit :
     95
     96|| RERROR          || code ||
     97||                         ||           ||
     98||READ_OK           || 00     ||
     99||WRITE_OK       || 10     ||
     100||READ_ERROR  || 01     ||
     101||WRITE_ERROR || 11     ||
     102   
     103
     104=== 3.3  DSPIN Packet format ===
    77105
    78106The VCI command & response packets are translated (actually serialized) to a more convenient DSPIN network format by appropriate wrappers located between the VCI initiator & target components and the DSPIN network. The DSPIN command packet width is 40 bits, and the DSPIN response packet width is 33 bits. The DSPIN interconnexion network use only the following information to route both the command and response packets to the proper destination (to a VCI target for a command packet, to a VCI initiator for a response packet) :
    … …  
    82110 * For a broadcast packet (BC = 1), the first flit contains the XMIN, XMAX, YMIN, YMAX fiels (5 bits each), that will be used by the network to limit the broadcast.
    83111
    84 ==== 3.1.1      DSPIN Read Command packet format  ====
     112==== 3.3.1      DSPIN Read Command packet format  ====
    85113
    86114A single flit VCI Read Command packet (this includes LL packets) is translated to a 2 flits DSPIN Read Command packet :
    … …  
    93121||1||   14   || 2    || 2    || 8     ||  4      || 4       || 5            ||
    94122
    95 ==== 3.1.2      DSPIN write Command packet format  ====
     123==== 3.3.2      DSPIN write Command packet format  ====
    96124
    97125A N flits VCI Write Command packet (this includes SC packets) is translated to a N+2 flits DSPIN Write Command packet :
    … …  
    107135||1||3               ||4 ||                               32                                           ||
    108136
    109 ==== 3.1.3      DSPIN Broadcast Command packet format ====
     137==== 3.3.3      DSPIN Broadcast Command packet format ====
    110138
    111139The single flit VCI Write Broadcast is translated to a 2 flits DSPIN Broadcast Command packet.
    … …  
    119147||1|| 5            ||                                      34                                                 ||
    120148
    121 ==== 3.1.4      DSPIN Read Response packet format ====
     149==== 3.3.4      DSPIN Read Response packet format ====
    122150
    123151A N flits VCI Read Response packet is translated to a N+1 flits DSPIN Read Response packet :
    … …  
    130158||1||                                      32                                                                 ||
    131159
    132 ==== 3.1.5      DSPIN Write response packet format ====
     160==== 3.3.5      DSPIN Write response packet format ====
    133161
    134162A single flit VCI Write Response packet is translated to a single flit DSPIN Write Response packet.
    … …  
    144172This network has a specific topology, as the communication scheme is very peculiar: All PUT/GET transactions are from N initiators (one initiator per cluster) to one single target (the external RAM controller).
    145173
     174=== 4.1 VCI parameters ===
     175
     176The external network, that is only transporting cache lines does not use all VCI fields. The
     177address is coded on 34 bits (it is actually a cache line index), and the data field is 64 bits,
     178to increase the bandwidth.
     179
     180|| VCI Field              ||  width  ||
     181||                              ||              ||
     182||ADDRESS                || 34 bits ||
     183||WDATA , RDATA || 64 bits ||
     184||PLEN                   || unused ||
     185||SRCID, RSRCID  || 10 bits ||
     186||TRDID, RTRDID  || 4 bits   ||
     187||PKTID, RPKTID || unused ||   
     188||RERROR                || 1 bit      ||       
    146189
    147190
    148191
    149192
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    151 
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