Changes between Version 17 and Version 18 of InterconnexionNetworks
- Timestamp:
- Jul 10, 2009, 10:45:22 AM (15 years ago)
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InterconnexionNetworks
v17 v18 15 15 == 2. VCI initiators & targets indexing == 16 16 17 As a given hardware component can have several VCI ports (for example the L1 cache has two VCI initiator ports : one port to the direct network, and one port to the coherence network), each VCI port should - in principle - have a different identifier. In the specific case of the TSAR architecture, a VCI target or initiator 17 As a given hardware component can have several VCI ports (for example the L1 cache has two VCI initiator ports : one port to the direct network, and one port to the coherence network), each VCI port should - in principle - have a different identifier. In the specific case of the TSAR architecture, a VCI target or initiator component will never have several VCI port of the same type (Initiator type or Target type) on the same network. Therefore, each hardware component has – for sake of simplicity - an absolute identifier that is defined by three indexes : 18 18 19 19 * '''X_ID''' is the cluster X-coordinate. … … 60 60 61 61 * The '''local interconnect''' is implemented as two physically independent local rings, and the coherence ring supports a broadcast service for single flit VCI commands. 62 Note : These two physically independ ant rings will be implemented later as one single physical ring supporting two virtual networks.62 Note : These two physically independent rings will be implemented later as one single physical ring supporting two virtual networks. 63 63 64 64 * The '''global interconnect''' is implemented as one DSPIN network, supporting two virtual sub-networks, and the coherence sub-network supports a broadcast service for single flit VCI commands. … … 104 104 === 3.3 DSPIN Packet format === 105 105 106 The VCI command & response packets are translated (actually serialized) to a more convenient DSPIN network format by appropriate wrappers located between the VCI initiator &target components and the DSPIN network. The DSPIN command packet width is 40 bits, and the DSPIN response packet width is 33 bits. The DSPIN interconnexion network use only the following information to route both the command and response packets to the proper destination (to a VCI target for a command packet, to a VCI initiator for a response packet) :106 The VCI command & response packets are translated (actually serialized) to a more convenient DSPIN network format by appropriate wrappers located between the VCI initiator and target components and the DSPIN network. The DSPIN command packet width is 40 bits, and the DSPIN response packet width is 33 bits. The DSPIN interconnexion network use only the following information to route both the command and response packets to the proper destination (to a VCI target for a command packet, to a VCI initiator for a response packet) : 107 107 * For both command and response packets, the MSB bit is the EOP flag (End of Packet). 108 108 * For a command packet, the LSB bit of the first flit (called BC) define a special broadcast command packet.