Changes between Version 2 and Version 3 of InterconnexionNetworks

Timestamp:

Jul 2, 2009, 4:40:43 PM (15 years ago)

Author:

alain

Comment:

--

InterconnexionNetworks

@@ -1 +1 @@
 [[PageOutline]]
 
-= Interconnection Networks =
+= Communication Infrastructure =
 
-== 1. The Three TSAR interconnection Networks ==
+== 1. The 3 interconnection Networks ==
+
 The TSAR architecture defines three logically independent VCI compliant networks, that are fully separated for dead-lock prevention :
  
--       The Direct Network implements the 40 bits TSAR physical address space that is visible by the software. It  transports the direct READ, WRITE, LL, & SC transactions from any VCI initiator (typically a L1 cache controller or another hardware coprocessor with a DMA capability) to any VCI target (typically a memory cache controller, or a memory mapped peripheral).
+ * The ''Direct Network'' implements the 40 bits TSAR physical address space that is visible by the software. It  transports the direct READ, WRITE, LL, & SC transactions from any VCI initiator (typically a L1 cache controller or another hardware coprocessor with a DMA capability) to any VCI target (typically a memory cache controller, or a memory mapped peripheral).
 
--       The Coherence Network implements a separated 40 bits physical address space, used to transport the coherence transactions : MULTI_UPDATE, MULTI_INVAL, BROADCAST_INVAL (from memory cache controllers to L1 cache controllers) and  CLEANUP (from the L1 cache controllers to the memory cache controllers). This address space is not visible by the software.
+ * The ''Coherence Network'' implements a separated 40 bits physical address space, used to transport the coherence transactions : MULTI_UPDATE, MULTI_INVAL, BROADCAST_INVAL (from memory cache controllers to L1 cache controllers) and  CLEANUP (from the L1 cache controllers to the memory cache controllers). This address space is not visible by the software.
 
--       The External Network implements a 40 bits physical address space.This network transports the PUT and GET transactions from the memory cache controller to the external RAM controller, in case of MISS or cache line replacement in the memory cache. This address space is not visible by the software. The 6 LSB bits of the VCI address are not used, as PUT & GET packets transport a 64 bytes aligned cache line.
-6.2     VCI Initiators & Targets Indexing
-As a given hardware component can have several VCI ports (for example the L1 cache has two VCI initiator ports to the direct network, and to the coherence network), each VCI port should have a different identifier. In the specific case of the TSAR architecture, a VCI target or initiator  component will never have several VCI port of the  same type on the same network. Therefore, each hardware component has – for sake of simplicity - an absolute identifier that is defined by three indexes :
+ * The External Network implements a 34 bits physical address space.This network transports the PUT and GET transactions from the memory cache controller to the external RAM controller, in case of MISS or cache line replacement in the memory cache. This address space is not visible by the software. 
 
--       X_INDEX is the cluster X-coordinate
--       Y_INDEX is the cluster Y-coordinate. be larger than 5.
--       LOCAL_INDEX is the local index inside the cluster.
+== 2.  VCI Initiators & Targets Indexing ==
+
+As a given hardware component can have several VCI ports (for example the L1 cache has two VCI initiator ports to the direct network, and to the coherence network), each VCI port should have a different identifier. In the specific case of the TSAR architecture, a VCI target or initiator  component will never have several VCI port of the  same type (Initiator type or Target type) on the same network. Therefore, each hardware component has – for sake of simplicity - an absolute identifier that is defined by three indexes :
+
+ * '''X_INDEX''' is the cluster X-coordinate.
+ * '''Y_INDEX'' is the cluster Y-coordinate. 
+ * '''LOCAL_INDEX''' is the local index inside the cluster.