Changes between Version 33 and Version 34 of InterconnexionNetworks

Timestamp:

Jun 1, 2011, 4:06:52 PM (14 years ago)

Author:

alain

Comment:

--

InterconnexionNetworks

@@ -68 +68 @@
 On the coherence network, the addresses are defined by the hardware with the following policy:
 
- * In a '''multicast''' command packet from a memory cache controller to a L1 cache controller, the address is obtained by copying the target L1 cache SRCID in the MSB bits of the VCI ADDRESS (left aligned) : The L1 cache L_ID is actually used as the LADR address field. UPDATE/INVAL requests are distinguished by the bit ADDRESS[2] (0 for INVAL, 1 for UPDATE).
+ * In a '''multicast''' command packet from a memory cache controller to a L1 cache controller, the address is obtained by copying the target L1 cache SRCID in the MSB bits of the VCI ADDRESS (left aligned) : The L1 cache L_ID is actually used as the LADR address field. UPDATE/INVAL requests are distinguished by the bit ADDRESS[3] (0 for INVAL, 1 for UPDATE). DATA/INSTRUCTION caches are distinguished by the bit ADDRESS[2] (0 for DATA, 1 for INSTRUCTION). 
 
  * In a '''cleanup''' command packet from a L1 cache controller to a memory cache controller, the address is obtained by copying the (NX + NY) MSB bits of the line address in the VCI ADDRESS field (left aligned). The 0 value for the LADR address field is used to select the memory cache.