64 | | There are 8 transaction types ('''READ_DATA_UNC''', '''READ_DATA_MISS''', '''READ_INS_UNC''', '''READ_INS_MISS''', '''WRITE''', '''CAS''', '''LL''', '''SC''') on the direct network. These types are encoded through the pair of VCI fields '''CMD''' and '''PKTID'''. The '''PKTID''' field in TSAR is 4 bits long, but the MSB is ignored (reserved for future use). |
| 64 | All Hardware components connected to the direct network respect the VCI/OCP communication interface. |
| 65 | |
| 66 | || VCI Field || width || |
| 67 | || || || |
| 68 | ||ADDRESS || 40 bits || |
| 69 | ||WDATA , RDATA || 32 bits || |
| 70 | ||PLEN || 8 bits || |
| 71 | ||SRCID, RSRCID || 14 bits || |
| 72 | ||TRDID, RTRDID || 4 bits || |
| 73 | ||PKTID, RPKTID || 4 bits || |
| 74 | ||RERROR || 1 bit || |
| 75 | |
| 76 | The TSAR architecture uses one single bit for the VCI RERROR field, even if the DSPIN infrastructure supports 2 bits for the error field. |
| 77 | |
| 78 | There are 8 transaction types on the direct network: '''READ_DATA_UNC''', '''READ_DATA_MISS''', '''READ_INS_UNC''', '''READ_INS_MISS''', '''WRITE''', '''CAS''', '''LL''', '''SC'''. These types are encoded through the VCI fields '''CMD''' and '''PKTID'''. The '''PKTID''' field in TSAR is 4 bits long, but the MSB is ignored (reserved for future use). |
157 | | === 3.3 VCI parameters === |
158 | | |
159 | | All Hardware components connected to the direct network or to the coherence network respect the VCI/OCP communication interface. |
160 | | |
161 | | The direct network, and the coherence network being ''time-multiplexed'' on the DSPIN infrastructure, have identical VCI formats : |
162 | | |
163 | | || VCI Field || width || |
164 | | || || || |
165 | | ||ADDRESS || 40 bits || |
166 | | ||WDATA , RDATA || 32 bits || |
167 | | ||PLEN || 8 bits || |
168 | | ||SRCID, RSRCID || 14 bits || |
169 | | ||TRDID, RTRDID || 4 bits || |
170 | | ||PKTID, RPKTID || 4 bits || |
171 | | ||RERROR || 1 bit || |
172 | | |
173 | | The TSAR architecture uses one single bit for the VCI RERROR field, even if the DSPIN infrastructure supports 2 bits for the error field. |
174 | | |
175 | | |
176 | | === 3.3 DSPIN Packet format === |
177 | | |
178 | | The VCI command & response packets are translated (actually serialized) to a more convenient DSPIN network format by the VCI/RING wrappers (in platform using the RING local interconnect) or by the VCI/DSPIN wrappers (in platforms using the XBAR local interconnect). These wrappers are located between the VCI initiator and target components and the DSPIN network. The DSPIN command packet width is 40 bits, and the DSPIN response packet width is 33 bits. The DSPIN interconnexion network uses only the following information to route both the DSPIN packets to the proper destination: |
| 171 | |
| 172 | === 3.2 DSPIN encoding of the various transaction types on the direct network === |
| 173 | |
| 174 | The VCI command & response packets are translated (actually serialized) to a more convenient DSPIN network format by the VCI/RING wrappers (in platform using the RING local interconnect) or by the VCI/DSPIN wrappers (in platforms using a XBAR local interconnect). These wrappers are located between the VCI initiator and target components and the DSPIN network. The DSPIN command packet width is 40 bits, and the DSPIN response packet width is 33 bits. The DSPIN interconnexion network uses only the following information to route both the DSPIN packets to the proper destination: |